/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn0_wf_tmac_top.h
//[Revision time]   : Fri Sep 28 11:45:53 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN0_WF_TMAC_TOP_REGS_H__
#define __BN0_WF_TMAC_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN0_WF_TMAC_TOP CR Definitions                     
//
//****************************************************************************

#define BN0_WF_TMAC_TOP_BASE                                   0x820E4000

#define BN0_WF_TMAC_TOP_TCR0_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x00) // 4000
#define BN0_WF_TMAC_TOP_PSCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x04) // 4004
#define BN0_WF_TMAC_TOP_ACTXOPLR0_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x10) // 4010
#define BN0_WF_TMAC_TOP_ACTXOPLR1_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x14) // 4014
#define BN0_WF_TMAC_TOP_ACTXOPLR2_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x18) // 4018
#define BN0_WF_TMAC_TOP_ACTXOPLR3_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x1C) // 401C
#define BN0_WF_TMAC_TOP_FP0R0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x20) // 4020
#define BN0_WF_TMAC_TOP_FP0R1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x24) // 4024
#define BN0_WF_TMAC_TOP_FP0R2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x28) // 4028
#define BN0_WF_TMAC_TOP_FP0R3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x2C) // 402C
#define BN0_WF_TMAC_TOP_FP0R4_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x30) // 4030
#define BN0_WF_TMAC_TOP_FP0R5_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x34) // 4034
#define BN0_WF_TMAC_TOP_FP0R6_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x38) // 4038
#define BN0_WF_TMAC_TOP_FP0R7_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x3C) // 403C
#define BN0_WF_TMAC_TOP_FP0R8_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x40) // 4040
#define BN0_WF_TMAC_TOP_FP0R9_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x44) // 4044
#define BN0_WF_TMAC_TOP_FP0R10_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x48) // 4048
#define BN0_WF_TMAC_TOP_FP0R11_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x4C) // 404C
#define BN0_WF_TMAC_TOP_FP0R12_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x50) // 4050
#define BN0_WF_TMAC_TOP_FP0R13_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x54) // 4054
#define BN0_WF_TMAC_TOP_FP0R14_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x58) // 4058
#define BN0_WF_TMAC_TOP_TCR2_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x5C) // 405C
#define BN0_WF_TMAC_TOP_ACTXOPLR4_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x60) // 4060
#define BN0_WF_TMAC_TOP_ACTXOPLR5_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x64) // 4064
#define BN0_WF_TMAC_TOP_ACTXOPLR6_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x68) // 4068
#define BN0_WF_TMAC_TOP_ACTXOPLR7_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x6C) // 406C
#define BN0_WF_TMAC_TOP_FP0R15_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x80) // 4080
#define BN0_WF_TMAC_TOP_FP0R16_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x84) // 4084
#define BN0_WF_TMAC_TOP_FP0R17_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x88) // 4088
#define BN0_WF_TMAC_TOP_TRCR2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x8C) // 408C
#define BN0_WF_TMAC_TOP_CDTR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x90) // 4090
#define BN0_WF_TMAC_TOP_ODTR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x94) // 4094
#define BN0_WF_TMAC_TOP_ATCR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x98) // 4098
#define BN0_WF_TMAC_TOP_TRCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x9C) // 409C
#define BN0_WF_TMAC_TOP_RRCR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0xA0) // 40A0
#define BN0_WF_TMAC_TOP_ICR0_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0xA4) // 40A4
#define BN0_WF_TMAC_TOP_PPDR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0xA8) // 40A8
#define BN0_WF_TMAC_TOP_BCSR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0xAC) // 40AC
#define BN0_WF_TMAC_TOP_BRCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xB0) // 40B0
#define BN0_WF_TMAC_TOP_BRCR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xB8) // 40B8
#define BN0_WF_TMAC_TOP_B0BRR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xC0) // 40C0
#define BN0_WF_TMAC_TOP_B0BRR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xC4) // 40C4
#define BN0_WF_TMAC_TOP_B1BRR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xC8) // 40C8
#define BN0_WF_TMAC_TOP_B1BRR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xCC) // 40CC
#define BN0_WF_TMAC_TOP_B2BRR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xD0) // 40D0
#define BN0_WF_TMAC_TOP_B2BRR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xD4) // 40D4
#define BN0_WF_TMAC_TOP_B3BRR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xD8) // 40D8
#define BN0_WF_TMAC_TOP_B3BRR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0xDC) // 40DC
#define BN0_WF_TMAC_TOP_QNCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xE0) // 40E0
#define BN0_WF_TMAC_TOP_QNCR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xE4) // 40E4
#define BN0_WF_TMAC_TOP_QNCR2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xE8) // 40E8
#define BN0_WF_TMAC_TOP_QNCR3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xEC) // 40EC
#define BN0_WF_TMAC_TOP_QNCR4_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xF0) // 40F0
#define BN0_WF_TMAC_TOP_CTCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xF4) // 40F4
#define BN0_WF_TMAC_TOP_CTCR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xF8) // 40F8
#define BN0_WF_TMAC_TOP_OMDTR_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0xFC) // 40FC
#define BN0_WF_TMAC_TOP_B0BRR4_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x108) // 4108
#define BN0_WF_TMAC_TOP_B1BRR2_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x110) // 4110
#define BN0_WF_TMAC_TOP_B2BRR2_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x114) // 4114
#define BN0_WF_TMAC_TOP_B3BRR2_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x118) // 4118
#define BN0_WF_TMAC_TOP_SPCR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x11C) // 411C
#define BN0_WF_TMAC_TOP_DBGR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x120) // 4120
#define BN0_WF_TMAC_TOP_DBGR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x124) // 4124
#define BN0_WF_TMAC_TOP_DBGR2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x128) // 4128
#define BN0_WF_TMAC_TOP_DBGR3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x12C) // 412C
#define BN0_WF_TMAC_TOP_DBGR4_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x130) // 4130
#define BN0_WF_TMAC_TOP_DBGR5_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x134) // 4134
#define BN0_WF_TMAC_TOP_DBGR6_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x138) // 4138
#define BN0_WF_TMAC_TOP_DBGR7_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x13C) // 413C
#define BN0_WF_TMAC_TOP_DBGR8_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x140) // 4140
#define BN0_WF_TMAC_TOP_DBGR9_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x144) // 4144
#define BN0_WF_TMAC_TOP_DBGR10_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x148) // 4148
#define BN0_WF_TMAC_TOP_DBGR11_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x14C) // 414C
#define BN0_WF_TMAC_TOP_DBGR12_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x150) // 4150
#define BN0_WF_TMAC_TOP_DBGR13_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x154) // 4154
#define BN0_WF_TMAC_TOP_DBGR14_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x158) // 4158
#define BN0_WF_TMAC_TOP_DBGR15_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x15C) // 415C
#define BN0_WF_TMAC_TOP_TFCR4_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x170) // 4170
#define BN0_WF_TMAC_TOP_TFCR5_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x174) // 4174
#define BN0_WF_TMAC_TOP_VHT_FP0CR_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x178) // 4178
#define BN0_WF_TMAC_TOP_THOCR_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x17C) // 417C
#define BN0_WF_TMAC_TOP_SACR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x180) // 4180
#define BN0_WF_TMAC_TOP_SACR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x184) // 4184
#define BN0_WF_TMAC_TOP_SACR2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x188) // 4188
#define BN0_WF_TMAC_TOP_SACR3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x18C) // 418C
#define BN0_WF_TMAC_TOP_TWCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x194) // 4194
#define BN0_WF_TMAC_TOP_SACR6_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x198) // 4198
#define BN0_WF_TMAC_TOP_DBGCTRL_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x19C) // 419C
#define BN0_WF_TMAC_TOP_DSWCR00_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1A0) // 41A0
#define BN0_WF_TMAC_TOP_DSWCR01_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1A4) // 41A4
#define BN0_WF_TMAC_TOP_DSWCR02_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1A8) // 41A8
#define BN0_WF_TMAC_TOP_DSWCR03_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1AC) // 41AC
#define BN0_WF_TMAC_TOP_DSWCR04_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1B0) // 41B0
#define BN0_WF_TMAC_TOP_DSWCR05_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1B4) // 41B4
#define BN0_WF_TMAC_TOP_DSWCR06_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1B8) // 41B8
#define BN0_WF_TMAC_TOP_DSWCR07_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x1BC) // 41BC
#define BN0_WF_TMAC_TOP_PPDR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x1C0) // 41C0
#define BN0_WF_TMAC_TOP_PPDR3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x1C8) // 41C8
#define BN0_WF_TMAC_TOP_TFCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x1E0) // 41E0
#define BN0_WF_TMAC_TOP_THOCR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x1E4) // 41E4
#define BN0_WF_TMAC_TOP_TFCR2_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x1E8) // 41E8
#define BN0_WF_TMAC_TOP_TFCR3_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x1EC) // 41EC
#define BN0_WF_TMAC_TOP_FPCR_ADDR                              (BN0_WF_TMAC_TOP_BASE + 0x23C) // 423C
#define BN0_WF_TMAC_TOP_DUCR0_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x240) // 4240
#define BN0_WF_TMAC_TOP_DUCR1_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x244) // 4244
#define BN0_WF_TMAC_TOP_BRVHTCR0_ADDR                          (BN0_WF_TMAC_TOP_BASE + 0x250) // 4250
#define BN0_WF_TMAC_TOP_BRVHTCR1_ADDR                          (BN0_WF_TMAC_TOP_BASE + 0x258) // 4258
#define BN0_WF_TMAC_TOP_BRHECR0_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x260) // 4260
#define BN0_WF_TMAC_TOP_BRHECR1_ADDR                           (BN0_WF_TMAC_TOP_BASE + 0x268) // 4268
#define BN0_WF_TMAC_TOP_FP0R18_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x270) // 4270
#define BN0_WF_TMAC_TOP_FP0R19_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x274) // 4274
#define BN0_WF_TMAC_TOP_FP0R20_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x278) // 4278
#define BN0_WF_TMAC_TOP_FP0R21_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x27C) // 427C
#define BN0_WF_TMAC_TOP_FP0R22_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x280) // 4280
#define BN0_WF_TMAC_TOP_FP0R23_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x284) // 4284
#define BN0_WF_TMAC_TOP_FP0R24_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x288) // 4288
#define BN0_WF_TMAC_TOP_FP0R25_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x28C) // 428C
#define BN0_WF_TMAC_TOP_FP0R26_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x290) // 4290
#define BN0_WF_TMAC_TOP_FP0R27_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x294) // 4294
#define BN0_WF_TMAC_TOP_FP0R28_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x298) // 4298
#define BN0_WF_TMAC_TOP_FP0R29_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x29C) // 429C
#define BN0_WF_TMAC_TOP_FP0R30_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2A0) // 42A0
#define BN0_WF_TMAC_TOP_FP0R31_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2A4) // 42A4
#define BN0_WF_TMAC_TOP_FP0R32_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2A8) // 42A8
#define BN0_WF_TMAC_TOP_FP0R33_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2AC) // 42AC
#define BN0_WF_TMAC_TOP_FP0R34_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2B0) // 42B0
#define BN0_WF_TMAC_TOP_FP0R35_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2B4) // 42B4
#define BN0_WF_TMAC_TOP_FP0R36_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2B8) // 42B8
#define BN0_WF_TMAC_TOP_FP0R37_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2BC) // 42BC
#define BN0_WF_TMAC_TOP_FP0R38_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2C0) // 42C0
#define BN0_WF_TMAC_TOP_FP0R39_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2C4) // 42C4
#define BN0_WF_TMAC_TOP_FP0R40_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x2C8) // 42C8
#define BN0_WF_TMAC_TOP_HE_FP0CR0_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x2D0) // 42D0
#define BN0_WF_TMAC_TOP_HE_FP0CR1_ADDR                         (BN0_WF_TMAC_TOP_BASE + 0x2D4) // 42D4
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2D8) // 42D8
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2DC) // 42DC
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2E0) // 42E0
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2E4) // 42E4
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2E8) // 42E8
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2EC) // 42EC
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2F0) // 42F0
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2F4) // 42F4
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2F8) // 42F8
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_ADDR                        (BN0_WF_TMAC_TOP_BASE + 0x2FC) // 42FC
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_ADDR                       (BN0_WF_TMAC_TOP_BASE + 0x300) // 4300
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_ADDR                       (BN0_WF_TMAC_TOP_BASE + 0x304) // 4304
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_ADDR                       (BN0_WF_TMAC_TOP_BASE + 0x308) // 4308
#define BN0_WF_TMAC_TOP_DUCR4_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x330) // 4330
#define BN0_WF_TMAC_TOP_SRTCR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x338) // 4338
#define BN0_WF_TMAC_TOP_TFCR6_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x340) // 4340
#define BN0_WF_TMAC_TOP_DUCR6_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x344) // 4344
#define BN0_WF_TMAC_TOP_DUCR7_ADDR                             (BN0_WF_TMAC_TOP_BASE + 0x348) // 4348
#define BN0_WF_TMAC_TOP_SRTCR2_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x34C) // 434C
#define BN0_WF_TMAC_TOP_SRTCR3_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x350) // 4350
#define BN0_WF_TMAC_TOP_SRTCR4_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x354) // 4354
#define BN0_WF_TMAC_TOP_SRTCR5_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x358) // 4358
#define BN0_WF_TMAC_TOP_SRTCR6_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x35C) // 435C
#define BN0_WF_TMAC_TOP_SRTCR7_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x360) // 4360
#define BN0_WF_TMAC_TOP_SRTCR8_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x364) // 4364
#define BN0_WF_TMAC_TOP_TTRCR0_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x370) // 4370
#define BN0_WF_TMAC_TOP_TTRCR1_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x374) // 4374
#define BN0_WF_TMAC_TOP_TTRCR2_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x378) // 4378
#define BN0_WF_TMAC_TOP_TTRCR3_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x37C) // 437C
#define BN0_WF_TMAC_TOP_TTRCR4_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x380) // 4380
#define BN0_WF_TMAC_TOP_TTRCR5_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x384) // 4384
#define BN0_WF_TMAC_TOP_TTRCR6_ADDR                            (BN0_WF_TMAC_TOP_BASE + 0x388) // 4388




/* =====================================================================================

  ---TCR0 (0x820E4000 + 0x00)---

    Reserved_TCR0_4[4..0]        - (RW) Reserved
    CTS_DYNBW_BW_SEL[5]          - (RW) Selects RX CTS responds dynamic BW
                                     1'b0: Select BW in scramble seed
                                     1'b1: Select BW in RX vector
    TX_BLINK_SEL[7..6]           - (RW) Selects TX blink mode
                                     2'b00: All TX frames
                                     2'b01: Exclude TX beacon and TIM broadcast frames
                                     2'b10: Only data frames
                                     Note: All three options exclude response control frames.
    Reserved_TCR0_3[9..8]        - (RW) Reserved
    CCA_RELD_AIFS[11..10]        - (RW) AIFS reload mode for CCA BUSY
                                     Bit[1]:
                                     1'b0: CCA_CS/CCA_PLD BUSY will not reload AIFS.
                                     1'b1: CCA_CS/CCS_PLD BUSY will reload AIFS.
                                     Bit[0]:
                                     1'b0: CCA_ED BUSY will not reload AIFS.
                                     1'b1: CCA_ED BUSY will reload AIFS.
    CTL_SIGTA_EN[12]             - (RW) Enables control frame signaling TA
                                     1'b0: Disable
                                     1'b1: Enable (The current chip is a VHT STA.)
    NDPA_SIGTA_EN[13]            - (RW) Enables NDPA signaling TA
                                     1'b0: Disable
                                     1'b1: Enable (The current chip is a VHT STA.)
    RTS_SIGTA_EN[14]             - (RW) Enables RTS signaling TA
                                     1'b0: Disable
                                     1'b1: Enable (The current chip is a VHT STA.)
    BFRPOLL_SIGTA_EN[15]         - (RW) Enables Beamform Report Poll signaling TA
                                     1'b0: Disable
                                     1'b1: Enable (The current chip is a VHT STA.)
    Reserved_TCR0_2[21..16]      - (RW) Reserved
    TX_RIFS_EN[22]               - (RW) Enables TX RIFS
                                     1'b0: Disable TX RIFS
                                     1'b1: Enable TX RIFS
    Reserved_TCR0_1[23]          - (RW) Reserved
    TXOP_TBTT_CONTROL[24]        - (RW) TBTT TXOP burst control
                                     This field controls the TXOP duration calculation when TBTT time is within the current packet period. This bit is only valid when PROTECTION_MODE is set to 1 (single protection mode).
                                     1'b0: TXOP will only include the current packet.
                                     1'b1: TXOP will include the packet behind the current packet if PROTECTION_MODE is set to 1.
    TBTT_TX_STOP_CONTROL[25]     - (RW) TBTT TX stop control
                                     This bit controls TXOP TBTT stop function.
                                     1'b0: TXOP will not be stopped if TX exchange time is over TBTT time.
                                     1'b1: TXOP will be stopped if TX exchange time is over TBTT time.
    Reserved_TCR0_0[26]          - (RW) Reserved
    RDG_RA_MODE[27]              - (RW) SelectS RDG compliant mode
                                     1'b0: specification mode
                                     1'b1: RA mode
    RDG_RESP_EN[28]              - (RW) Enables RDG responder
                                     1'b0: Disable RDG responder. After receivingthe grant PPDU from RDG initiator, MT6620 will not be the RDG responder. 
                                     1'b1: Enable RDG responder. After receiving the grant PPDU from RDG initiator, MT6620 will be the RDG responder if there are frames to be transferred.
    Reserved_TCR0_5[29]          - (RW) Reserved
    BEAM_CHANGE_FORCE[30]        - (RW) Force Beam Change to 1 for HE_SU  / HE_ERSU
                                     1'b1: force beam change to 1
                                     1'b0: follow the original value
    Smoothing[31]                - (RW) Enables TX smoothing
                                     This field indicates BBP is to set up the smoothing bit in HT-SIG of HT MM or GF packet transmission.
                                     1'b1: Set smoothing bit = 1
                                     1'b0: Set smoothing bit = 0

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TCR0_Smoothing_ADDR                    BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Smoothing_MASK                    0x80000000                // Smoothing[31]
#define BN0_WF_TMAC_TOP_TCR0_Smoothing_SHFT                    31
#define BN0_WF_TMAC_TOP_TCR0_BEAM_CHANGE_FORCE_ADDR            BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_BEAM_CHANGE_FORCE_MASK            0x40000000                // BEAM_CHANGE_FORCE[30]
#define BN0_WF_TMAC_TOP_TCR0_BEAM_CHANGE_FORCE_SHFT            30
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_5_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_5_MASK              0x20000000                // Reserved_TCR0_5[29]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_5_SHFT              29
#define BN0_WF_TMAC_TOP_TCR0_RDG_RESP_EN_ADDR                  BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_RDG_RESP_EN_MASK                  0x10000000                // RDG_RESP_EN[28]
#define BN0_WF_TMAC_TOP_TCR0_RDG_RESP_EN_SHFT                  28
#define BN0_WF_TMAC_TOP_TCR0_RDG_RA_MODE_ADDR                  BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_RDG_RA_MODE_MASK                  0x08000000                // RDG_RA_MODE[27]
#define BN0_WF_TMAC_TOP_TCR0_RDG_RA_MODE_SHFT                  27
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_0_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_0_MASK              0x04000000                // Reserved_TCR0_0[26]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_0_SHFT              26
#define BN0_WF_TMAC_TOP_TCR0_TBTT_TX_STOP_CONTROL_ADDR         BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_TBTT_TX_STOP_CONTROL_MASK         0x02000000                // TBTT_TX_STOP_CONTROL[25]
#define BN0_WF_TMAC_TOP_TCR0_TBTT_TX_STOP_CONTROL_SHFT         25
#define BN0_WF_TMAC_TOP_TCR0_TXOP_TBTT_CONTROL_ADDR            BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_TXOP_TBTT_CONTROL_MASK            0x01000000                // TXOP_TBTT_CONTROL[24]
#define BN0_WF_TMAC_TOP_TCR0_TXOP_TBTT_CONTROL_SHFT            24
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_1_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_1_MASK              0x00800000                // Reserved_TCR0_1[23]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_1_SHFT              23
#define BN0_WF_TMAC_TOP_TCR0_TX_RIFS_EN_ADDR                   BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_TX_RIFS_EN_MASK                   0x00400000                // TX_RIFS_EN[22]
#define BN0_WF_TMAC_TOP_TCR0_TX_RIFS_EN_SHFT                   22
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_2_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_2_MASK              0x003F0000                // Reserved_TCR0_2[21..16]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_2_SHFT              16
#define BN0_WF_TMAC_TOP_TCR0_BFRPOLL_SIGTA_EN_ADDR             BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_BFRPOLL_SIGTA_EN_MASK             0x00008000                // BFRPOLL_SIGTA_EN[15]
#define BN0_WF_TMAC_TOP_TCR0_BFRPOLL_SIGTA_EN_SHFT             15
#define BN0_WF_TMAC_TOP_TCR0_RTS_SIGTA_EN_ADDR                 BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_RTS_SIGTA_EN_MASK                 0x00004000                // RTS_SIGTA_EN[14]
#define BN0_WF_TMAC_TOP_TCR0_RTS_SIGTA_EN_SHFT                 14
#define BN0_WF_TMAC_TOP_TCR0_NDPA_SIGTA_EN_ADDR                BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_NDPA_SIGTA_EN_MASK                0x00002000                // NDPA_SIGTA_EN[13]
#define BN0_WF_TMAC_TOP_TCR0_NDPA_SIGTA_EN_SHFT                13
#define BN0_WF_TMAC_TOP_TCR0_CTL_SIGTA_EN_ADDR                 BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_CTL_SIGTA_EN_MASK                 0x00001000                // CTL_SIGTA_EN[12]
#define BN0_WF_TMAC_TOP_TCR0_CTL_SIGTA_EN_SHFT                 12
#define BN0_WF_TMAC_TOP_TCR0_CCA_RELD_AIFS_ADDR                BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_CCA_RELD_AIFS_MASK                0x00000C00                // CCA_RELD_AIFS[11..10]
#define BN0_WF_TMAC_TOP_TCR0_CCA_RELD_AIFS_SHFT                10
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_3_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_3_MASK              0x00000300                // Reserved_TCR0_3[9..8]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_3_SHFT              8
#define BN0_WF_TMAC_TOP_TCR0_TX_BLINK_SEL_ADDR                 BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_TX_BLINK_SEL_MASK                 0x000000C0                // TX_BLINK_SEL[7..6]
#define BN0_WF_TMAC_TOP_TCR0_TX_BLINK_SEL_SHFT                 6
#define BN0_WF_TMAC_TOP_TCR0_CTS_DYNBW_BW_SEL_ADDR             BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_CTS_DYNBW_BW_SEL_MASK             0x00000020                // CTS_DYNBW_BW_SEL[5]
#define BN0_WF_TMAC_TOP_TCR0_CTS_DYNBW_BW_SEL_SHFT             5
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_4_ADDR              BN0_WF_TMAC_TOP_TCR0_ADDR
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_4_MASK              0x0000001F                // Reserved_TCR0_4[4..0]
#define BN0_WF_TMAC_TOP_TCR0_Reserved_TCR0_4_SHFT              0

/* =====================================================================================

  ---PSCR0 (0x820E4000 + 0x04)---

    RESERVED0[0]                 - (RO) Reserved bits
    APS_OFF_TIME[8..1]           - (RW) AP power saving RXPE off time
                                     Unit: 2us; max. time: 510us
                                     1'b0: 0us
                                     1'b1: 2us and so on
                                     The accuracy is -1us ~ 0us.
    RESERVED9[9]                 - (RO) Reserved bits
    APS_ON_TIME[15..10]          - (RW) AP power saving RXPE on time
                                     Unit: 2us; max. time: 126us
                                     1'b0: 0us
                                     1'b1: 2us and so on
                                     The accuracy is -1us ~ 0us.
    APS_HALT_TIME[25..16]        - (RW) AP power saving halt time
                                     RXPE will work as normal operation.
                                     Unit: 32us; max. time: ~32ms
                                     1'b0: 0us
                                     1'b1: 32us and so on
                                     The accruacy is -32us ~ 0us.
    RESERVED26[26]               - (RO) Reserved bits
    APS_ACT_STS[27]              - (RO) AP active status
                                     0: GreenAP state machine is not active.
                                     1: GreenAP state machine is active.
    APS_EN[28]                   - (RW) AP power saving mode enable control
                                     1'b0: Disable
                                     1'b1: Enable
    APS_OFF_MODE[29]             - (RW) Selects AP OFF mode
                                     1'b0: Disable BBP only during OFF period
                                     1'b1: Disable BBP & RF SX during OFF period
    APS_DIS_RX_STS[30]           - (RO) AP disable RX status
                                     0: BBP RX is not disabled by GreenAP.
                                     1: BBP RX is disabled by GreenAP.
    APS_DIS_SX_STS[31]           - (RO) AP disable SX status
                                     0: SX is not disabled by GreenAP.
                                     1: SX is disabled by GreenAP

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_SX_STS_ADDR              BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_SX_STS_MASK              0x80000000                // APS_DIS_SX_STS[31]
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_SX_STS_SHFT              31
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_RX_STS_ADDR              BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_RX_STS_MASK              0x40000000                // APS_DIS_RX_STS[30]
#define BN0_WF_TMAC_TOP_PSCR0_APS_DIS_RX_STS_SHFT              30
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_MODE_ADDR                BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_MODE_MASK                0x20000000                // APS_OFF_MODE[29]
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_MODE_SHFT                29
#define BN0_WF_TMAC_TOP_PSCR0_APS_EN_ADDR                      BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_EN_MASK                      0x10000000                // APS_EN[28]
#define BN0_WF_TMAC_TOP_PSCR0_APS_EN_SHFT                      28
#define BN0_WF_TMAC_TOP_PSCR0_APS_ACT_STS_ADDR                 BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_ACT_STS_MASK                 0x08000000                // APS_ACT_STS[27]
#define BN0_WF_TMAC_TOP_PSCR0_APS_ACT_STS_SHFT                 27
#define BN0_WF_TMAC_TOP_PSCR0_APS_HALT_TIME_ADDR               BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_HALT_TIME_MASK               0x03FF0000                // APS_HALT_TIME[25..16]
#define BN0_WF_TMAC_TOP_PSCR0_APS_HALT_TIME_SHFT               16
#define BN0_WF_TMAC_TOP_PSCR0_APS_ON_TIME_ADDR                 BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_ON_TIME_MASK                 0x0000FC00                // APS_ON_TIME[15..10]
#define BN0_WF_TMAC_TOP_PSCR0_APS_ON_TIME_SHFT                 10
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_TIME_ADDR                BN0_WF_TMAC_TOP_PSCR0_ADDR
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_TIME_MASK                0x000001FE                // APS_OFF_TIME[8..1]
#define BN0_WF_TMAC_TOP_PSCR0_APS_OFF_TIME_SHFT                1

/* =====================================================================================

  ---ACTXOPLR0 (0x820E4000 + 0x10)---

    AC02LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC03LIMIT[31..16]            - (RW) The TXOP limit of AC03 for EDCA when granting the TXOP. 0 means only one MSDU can be transmitted in granted TXOP. 
                                     Note: The unit is 32us.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC03LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR0_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC03LIMIT_MASK               0xFFFF0000                // AC03LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC03LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC02LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR0_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC02LIMIT_MASK               0x0000FFFF                // AC02LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR0_AC02LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR1 (0x820E4000 + 0x14)---

    AC00LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC01LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC01LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR1_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC01LIMIT_MASK               0xFFFF0000                // AC01LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC01LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC00LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR1_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC00LIMIT_MASK               0x0000FFFF                // AC00LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR1_AC00LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR2 (0x820E4000 + 0x18)---

    AC12LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC13LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC13LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR2_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC13LIMIT_MASK               0xFFFF0000                // AC13LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC13LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC12LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR2_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC12LIMIT_MASK               0x0000FFFF                // AC12LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR2_AC12LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR3 (0x820E4000 + 0x1C)---

    AC10LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC11LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC11LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR3_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC11LIMIT_MASK               0xFFFF0000                // AC11LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC11LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC10LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR3_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC10LIMIT_MASK               0x0000FFFF                // AC10LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR3_AC10LIMIT_SHFT               0

/* =====================================================================================

  ---FP0R0 (0x820E4000 + 0x20)---

    CCK0_FRAME_POWER_DBM[7..0]   - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For CCK 1M rates.
    CCK1_FRAME_POWER_DBM[15..8]  - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For CCK 2M rates.
    CCK2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For CCK 5.5M rates.
    CCK3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For CCK 11M rates.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R0_CCK3_FRAME_POWER_DBM_ADDR        BN0_WF_TMAC_TOP_FP0R0_ADDR
#define BN0_WF_TMAC_TOP_FP0R0_CCK3_FRAME_POWER_DBM_MASK        0xFF000000                // CCK3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R0_CCK3_FRAME_POWER_DBM_SHFT        24
#define BN0_WF_TMAC_TOP_FP0R0_CCK2_FRAME_POWER_DBM_ADDR        BN0_WF_TMAC_TOP_FP0R0_ADDR
#define BN0_WF_TMAC_TOP_FP0R0_CCK2_FRAME_POWER_DBM_MASK        0x00FF0000                // CCK2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R0_CCK2_FRAME_POWER_DBM_SHFT        16
#define BN0_WF_TMAC_TOP_FP0R0_CCK1_FRAME_POWER_DBM_ADDR        BN0_WF_TMAC_TOP_FP0R0_ADDR
#define BN0_WF_TMAC_TOP_FP0R0_CCK1_FRAME_POWER_DBM_MASK        0x0000FF00                // CCK1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R0_CCK1_FRAME_POWER_DBM_SHFT        8
#define BN0_WF_TMAC_TOP_FP0R0_CCK0_FRAME_POWER_DBM_ADDR        BN0_WF_TMAC_TOP_FP0R0_ADDR
#define BN0_WF_TMAC_TOP_FP0R0_CCK0_FRAME_POWER_DBM_MASK        0x000000FF                // CCK0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R0_CCK0_FRAME_POWER_DBM_SHFT        0

/* =====================================================================================

  ---FP0R1 (0x820E4000 + 0x24)---

    LG_OFDM0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (Rate:6Mbps)
    LG_OFDM1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (Rate: 9Mbps)
    LG_OFDM2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (Rate:12Mbps)
    LG_OFDM3_FRAME_POWER_DBM[31..24] - (RW) Indicates TX power dBm
                                     Unit: 0.5dBm
                                     The encoding rule is 2's complement.
                                     7'b0000000: 0dBm
                                     7'b0000001: 0.5dBm
                                     7'b0111111: 31.5dBm
                                     7'b1111111: -0.5dBm
                                     7'b1000000: -32dBm
                                     For QPSK modulation. (Rate: 18Mbps)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R1_ADDR
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM3_FRAME_POWER_DBM_MASK    0xFF000000                // LG_OFDM3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R1_ADDR
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM2_FRAME_POWER_DBM_MASK    0x00FF0000                // LG_OFDM2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R1_ADDR
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM1_FRAME_POWER_DBM_MASK    0x0000FF00                // LG_OFDM1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R1_ADDR
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM0_FRAME_POWER_DBM_MASK    0x000000FF                // LG_OFDM0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R1_LG_OFDM0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R2 (0x820E4000 + 0x28)---

    LG_OFDM4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM4_FRAME_POWER_DBM
                                     For 16-QAM modulation. (Rate:24Mbps)
    LG_OFDM5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM5_FRAME_POWER_DBM
                                     For 16-QAM modulation. (Rate: 36Mbps)
    LG_OFDM6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM6_FRAME_POWER_DBM
                                     For 64-QAM modulation. (Rate:48Mbps)
    LG_OFDM7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM7_FRAME_POWER_DBM
                                     For 64-QAM modulation. (Rate: 54Mbps)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R2_ADDR
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM7_FRAME_POWER_DBM_MASK    0xFF000000                // LG_OFDM7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R2_ADDR
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM6_FRAME_POWER_DBM_MASK    0x00FF0000                // LG_OFDM6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R2_ADDR
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM5_FRAME_POWER_DBM_MASK    0x0000FF00                // LG_OFDM5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R2_ADDR
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM4_FRAME_POWER_DBM_MASK    0x000000FF                // LG_OFDM4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R2_LG_OFDM4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R3 (0x820E4000 + 0x2C)---

    HT20_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0/MCS8/MCS16/MCS24)
    HT20_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1/MCS9/MCS17/MCS25)
    HT20_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2/MCS10/MCS18/MCS26)
    HT20_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation (MCS3/MCS11/MCS19/MCS26)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R3_HT20_3_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R3_ADDR
#define BN0_WF_TMAC_TOP_FP0R3_HT20_3_FRAME_POWER_DBM_MASK      0xFF000000                // HT20_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R3_HT20_3_FRAME_POWER_DBM_SHFT      24
#define BN0_WF_TMAC_TOP_FP0R3_HT20_2_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R3_ADDR
#define BN0_WF_TMAC_TOP_FP0R3_HT20_2_FRAME_POWER_DBM_MASK      0x00FF0000                // HT20_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R3_HT20_2_FRAME_POWER_DBM_SHFT      16
#define BN0_WF_TMAC_TOP_FP0R3_HT20_1_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R3_ADDR
#define BN0_WF_TMAC_TOP_FP0R3_HT20_1_FRAME_POWER_DBM_MASK      0x0000FF00                // HT20_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R3_HT20_1_FRAME_POWER_DBM_SHFT      8
#define BN0_WF_TMAC_TOP_FP0R3_HT20_0_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R3_ADDR
#define BN0_WF_TMAC_TOP_FP0R3_HT20_0_FRAME_POWER_DBM_MASK      0x000000FF                // HT20_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R3_HT20_0_FRAME_POWER_DBM_SHFT      0

/* =====================================================================================

  ---FP0R4 (0x820E4000 + 0x30)---

    HT20_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation MCS4/MCS12/MCS20/MCS28 rate.
    HT20_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS5/MCS13/MCS21/MCS29 rate.
    HT20_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS6/MCS14/MCS22/MCS30 rate.
    HT20_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS7/MCS15/MCS23/MCS31rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R4_HT20_7_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R4_ADDR
#define BN0_WF_TMAC_TOP_FP0R4_HT20_7_FRAME_POWER_DBM_MASK      0xFF000000                // HT20_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R4_HT20_7_FRAME_POWER_DBM_SHFT      24
#define BN0_WF_TMAC_TOP_FP0R4_HT20_6_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R4_ADDR
#define BN0_WF_TMAC_TOP_FP0R4_HT20_6_FRAME_POWER_DBM_MASK      0x00FF0000                // HT20_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R4_HT20_6_FRAME_POWER_DBM_SHFT      16
#define BN0_WF_TMAC_TOP_FP0R4_HT20_5_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R4_ADDR
#define BN0_WF_TMAC_TOP_FP0R4_HT20_5_FRAME_POWER_DBM_MASK      0x0000FF00                // HT20_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R4_HT20_5_FRAME_POWER_DBM_SHFT      8
#define BN0_WF_TMAC_TOP_FP0R4_HT20_4_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R4_ADDR
#define BN0_WF_TMAC_TOP_FP0R4_HT20_4_FRAME_POWER_DBM_MASK      0x000000FF                // HT20_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R4_HT20_4_FRAME_POWER_DBM_SHFT      0

/* =====================================================================================

  ---FP0R5 (0x820E4000 + 0x34)---

    HT40_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0/MCS8/MCS16/MCS24)
    HT40_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1/MCS9/MCS17/MCS25)
    HT40_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2/MCS10/MCS18/MCS26)
    HT40_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation (MCS3/MCS11/MCS19/MCS26)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R5_HT40_3_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R5_ADDR
#define BN0_WF_TMAC_TOP_FP0R5_HT40_3_FRAME_POWER_DBM_MASK      0xFF000000                // HT40_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R5_HT40_3_FRAME_POWER_DBM_SHFT      24
#define BN0_WF_TMAC_TOP_FP0R5_HT40_2_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R5_ADDR
#define BN0_WF_TMAC_TOP_FP0R5_HT40_2_FRAME_POWER_DBM_MASK      0x00FF0000                // HT40_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R5_HT40_2_FRAME_POWER_DBM_SHFT      16
#define BN0_WF_TMAC_TOP_FP0R5_HT40_1_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R5_ADDR
#define BN0_WF_TMAC_TOP_FP0R5_HT40_1_FRAME_POWER_DBM_MASK      0x0000FF00                // HT40_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R5_HT40_1_FRAME_POWER_DBM_SHFT      8
#define BN0_WF_TMAC_TOP_FP0R5_HT40_0_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R5_ADDR
#define BN0_WF_TMAC_TOP_FP0R5_HT40_0_FRAME_POWER_DBM_MASK      0x000000FF                // HT40_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R5_HT40_0_FRAME_POWER_DBM_SHFT      0

/* =====================================================================================

  ---FP0R6 (0x820E4000 + 0x38)---

    HT40_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation MCS4/MCS12/MCS20/MCS28 rate.
    HT40_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS5/MCS13/MCS21/MCS29 rate.
    HT40_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS6/MCS14/MCS22/MCS30 rate.
    HT40_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation MCS7/MCS15/MCS23/MCS31rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R6_HT40_7_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R6_ADDR
#define BN0_WF_TMAC_TOP_FP0R6_HT40_7_FRAME_POWER_DBM_MASK      0xFF000000                // HT40_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R6_HT40_7_FRAME_POWER_DBM_SHFT      24
#define BN0_WF_TMAC_TOP_FP0R6_HT40_6_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R6_ADDR
#define BN0_WF_TMAC_TOP_FP0R6_HT40_6_FRAME_POWER_DBM_MASK      0x00FF0000                // HT40_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R6_HT40_6_FRAME_POWER_DBM_SHFT      16
#define BN0_WF_TMAC_TOP_FP0R6_HT40_5_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R6_ADDR
#define BN0_WF_TMAC_TOP_FP0R6_HT40_5_FRAME_POWER_DBM_MASK      0x0000FF00                // HT40_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R6_HT40_5_FRAME_POWER_DBM_SHFT      8
#define BN0_WF_TMAC_TOP_FP0R6_HT40_4_FRAME_POWER_DBM_ADDR      BN0_WF_TMAC_TOP_FP0R6_ADDR
#define BN0_WF_TMAC_TOP_FP0R6_HT40_4_FRAME_POWER_DBM_MASK      0x000000FF                // HT40_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R6_HT40_4_FRAME_POWER_DBM_SHFT      0

/* =====================================================================================

  ---FP0R7 (0x820E4000 + 0x3C)---

    VHT20_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    VHT20_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    VHT20_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    VHT20_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_3_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R7_ADDR
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_3_FRAME_POWER_DBM_MASK     0xFF000000                // VHT20_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_3_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_2_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R7_ADDR
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_2_FRAME_POWER_DBM_MASK     0x00FF0000                // VHT20_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_2_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_1_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R7_ADDR
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_1_FRAME_POWER_DBM_MASK     0x0000FF00                // VHT20_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_1_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_0_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R7_ADDR
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_0_FRAME_POWER_DBM_MASK     0x000000FF                // VHT20_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R7_VHT20_0_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R8 (0x820E4000 + 0x40)---

    VHT20_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    VHT20_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    VHT20_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    VHT20_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_7_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R8_ADDR
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_7_FRAME_POWER_DBM_MASK     0xFF000000                // VHT20_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_7_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_6_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R8_ADDR
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_6_FRAME_POWER_DBM_MASK     0x00FF0000                // VHT20_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_6_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_5_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R8_ADDR
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_5_FRAME_POWER_DBM_MASK     0x0000FF00                // VHT20_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_5_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_4_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R8_ADDR
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_4_FRAME_POWER_DBM_MASK     0x000000FF                // VHT20_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R8_VHT20_4_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R9 (0x820E4000 + 0x44)---

    VHT20_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    VHT20_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    VHT40_0_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    VHT40_1_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_1_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R9_ADDR
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_1_FRAME_POWER_DBM_MASK     0xFF000000                // VHT40_1_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_1_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_0_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R9_ADDR
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_0_FRAME_POWER_DBM_MASK     0x00FF0000                // VHT40_0_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R9_VHT40_0_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_9_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R9_ADDR
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_9_FRAME_POWER_DBM_MASK     0x0000FF00                // VHT20_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_9_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_8_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R9_ADDR
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_8_FRAME_POWER_DBM_MASK     0x000000FF                // VHT20_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R9_VHT20_8_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R10 (0x820E4000 + 0x48)---

    VHT40_2_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    VHT40_3_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)
    VHT40_4_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    VHT40_5_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R10_ADDR
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_5_FRAME_POWER_DBM_MASK    0xFF000000                // VHT40_5_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_5_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R10_ADDR
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_4_FRAME_POWER_DBM_MASK    0x00FF0000                // VHT40_4_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_4_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R10_ADDR
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_3_FRAME_POWER_DBM_MASK    0x0000FF00                // VHT40_3_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_3_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R10_ADDR
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_2_FRAME_POWER_DBM_MASK    0x000000FF                // VHT40_2_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R10_VHT40_2_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R11 (0x820E4000 + 0x4C)---

    VHT40_6_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    VHT40_7_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)
    VHT40_8_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    VHT40_9_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R11_ADDR
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_9_FRAME_POWER_DBM_MASK    0xFF000000                // VHT40_9_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_9_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R11_ADDR
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_8_FRAME_POWER_DBM_MASK    0x00FF0000                // VHT40_8_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_8_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R11_ADDR
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_7_FRAME_POWER_DBM_MASK    0x0000FF00                // VHT40_7_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_7_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R11_ADDR
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_6_FRAME_POWER_DBM_MASK    0x000000FF                // VHT40_6_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R11_VHT40_6_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R12 (0x820E4000 + 0x50)---

    VHT80_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    VHT80_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    VHT80_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    VHT80_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R12_ADDR
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_3_FRAME_POWER_DBM_MASK    0xFF000000                // VHT80_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R12_ADDR
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_2_FRAME_POWER_DBM_MASK    0x00FF0000                // VHT80_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R12_ADDR
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_1_FRAME_POWER_DBM_MASK    0x0000FF00                // VHT80_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R12_ADDR
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_0_FRAME_POWER_DBM_MASK    0x000000FF                // VHT80_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R12_VHT80_0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R13 (0x820E4000 + 0x54)---

    VHT80_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    VHT80_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    VHT80_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    VHT80_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R13_ADDR
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_7_FRAME_POWER_DBM_MASK    0xFF000000                // VHT80_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R13_ADDR
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_6_FRAME_POWER_DBM_MASK    0x00FF0000                // VHT80_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R13_ADDR
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_5_FRAME_POWER_DBM_MASK    0x0000FF00                // VHT80_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R13_ADDR
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_4_FRAME_POWER_DBM_MASK    0x000000FF                // VHT80_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R13_VHT80_4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R14 (0x820E4000 + 0x58)---

    VHT80_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    VHT80_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    VHT160_0_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    VHT160_1_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_1_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R14_ADDR
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_1_FRAME_POWER_DBM_MASK   0xFF000000                // VHT160_1_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_1_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_0_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R14_ADDR
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_0_FRAME_POWER_DBM_MASK   0x00FF0000                // VHT160_0_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R14_VHT160_0_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R14_ADDR
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_9_FRAME_POWER_DBM_MASK    0x0000FF00                // VHT80_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_9_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R14_ADDR
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_8_FRAME_POWER_DBM_MASK    0x000000FF                // VHT80_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R14_VHT80_8_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---TCR2 (0x820E4000 + 0x5C)---

    HT_EXTLTF[1..0]              - (RW) HT extension LTF number
                                     (For BBP tests only)
    EDCCA_STOP_TRIGR[2]          - (RW) EDCCA stop RDG / Basic Trigger Frame / BQRP responder
                                     1'b0: EDCCA HIGH has no effect on RDG / TF responder.
                                     1'b1. EDCCA HIGH will stop RDG / TF responder.
    EDCCA_STOP_TXOP[3]           - (RW) EDCCA stop TXOP burst
                                     1'b0: EDCCA HIGH has no effect on TXOP burst.
                                     1'b1: EDCCA HIGH will stop TXOP burst.
    MAX_LG_LEN_CHK_EN[4]         - (RW) Enables maximum L-SIG length checker for HT-MM/VHT/HE PPDU
                                     Check if the calculated legacy length is longer than 4095. If it is true, the current TX will be aborted.
                                     0: Disable
                                     1: Enable
    MAX_PSDU_CHK_EN[5]           - (RW) Enables maximum PSDU checker
                                     Check if the calculated PPDU time is longer than max. PPDU time. If it is true, the current TX will be aborted.
                                     0: Disable
                                     1: Enable
    BKOF_APSOFF_OPT[6]           - (RW) Backoff MAC2PHY_RX status option
                                     0: Keep backoff counting down when GreenAP disables BBP RX
                                     1: Stop backoff counting down when GreenAP disables BBP RX
    BKOF_SX_OPT[7]               - (RW) Backoff SX status option
                                     0: Keep backoff counting down when SX is not ready
                                     1: Stop backoff counting down when SX is not ready
    LDPC_OFST_EN[8]              - (RW) Adds TXTime offset for LDPC TX
                                     1'b0: No offset
                                     1'b1: LDPC wo STBC; add 4us to duration
                                                LDPC wi STBC; add 8us to duration
    PRERTS_DET_DIS[9]            - (RW) Detects Pre-RTS idle
                                     1'b0: Enable detection
                                     1'b1: Disable detection
    PRE_RTS_SEC_IDLE_SEL[11..10] - (RW) Selects PRE_RTS second cnannel CCA IDLE
                                     2'b00: 1 SIFS
                                     2'b01: 1 SIFS + 1 SLOT
                                     2'b10: 1 SIFS + 2 SLOT
                                     2'b11: 1 SIFS + 3 SLOT
    PRE_RTS_DET_GUARD_TIME[15..12] - (RW) Detection guard time
                                     Used for de-bouncing CCA unstable period.
                                     Unit: 1us
                                     1'b0: 0us
                                     1'b1: 1us
                                     and so on.
                                     The persion (??) is 0~-1us.
    SCH_IDLE_SEL[17..16]         - (RW) Selects idle time for secondary channel is DIFS or PIFS
                                     2'b00: 1 SIFS
                                     2'b01: 1 SIFS + 1 slot (PIFS)
                                     2'b10: 1 SIFS + 2 slots (DIFS)
                                     2'b11: 1 SIFS + 3 slots
                                     Note: this CR also apply to non-primary per 20MHz sub-channel ED-CCA detection
    SCH_DET_PERIOD[18]           - (RW) Secondary channel CCA detection period
                                     1'b0: Check every clock cycle
                                     1'b1: Check by slot boundary
                                     Note: this CR also apply to non-primary per 20MHz sub-channel ED-CCA detection
    SCH_DET_DIS[19]              - (RW) Secondary channel CCA detectiond disable control
                                     1'b0: Enable secondary channel detection
                                     1'b1: Disable secondary channel detection; the channel status is always treated as idle.
                                     Note: this CR also apply to non-primary per 20MHz sub-channel ED-CCA detection
    Reserved_TCR2_0[26..20]      - (RW) Reserved
    SGI_SIG_ALIGN_EN[27]         - (RW) Select to enable or disable SGI Singal Extension Alignment
    TXOP_ABORT_OPT[28]           - (RW) TXOP Abort option
                                     0: TXOP abort is allowable
                                     1: TXOP abort is NOT allowable
    TXOP_BURST_STOP[29]          - (RW) Controls TXOP burst stop function
                                     0: TXOP will not be stopped at TX exchange time if the previous TX exchange time contains only 1 packet.
                                     1: TXOP will be stopped at TX exchange time if the previous TX exchange time contains only 1 packet.
    RX_RIFS_MODE[30]             - (RW) Enables RX RIFS
                                     1'b0: Control RF into standby mode for power saving due to there is no RIFS condition. 
                                     1'b1: Not control RF into standby mode for power saving due to RIFS condition.
    GRANT_REVERSE_WHEN_NO_PENDING_FRM[31] - (RW) Grant reverse when no pending frame
                                     1'b0: Grant reverse direction without checking if there is any pending frame waiting for transmission
                                     1'b1: No pending frame for transmission is a necessary checking criterion before granting reverse to the peer.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TCR2_GRANT_REVERSE_WHEN_NO_PENDING_FRM_ADDR BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_GRANT_REVERSE_WHEN_NO_PENDING_FRM_MASK 0x80000000                // GRANT_REVERSE_WHEN_NO_PENDING_FRM[31]
#define BN0_WF_TMAC_TOP_TCR2_GRANT_REVERSE_WHEN_NO_PENDING_FRM_SHFT 31
#define BN0_WF_TMAC_TOP_TCR2_RX_RIFS_MODE_ADDR                 BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_RX_RIFS_MODE_MASK                 0x40000000                // RX_RIFS_MODE[30]
#define BN0_WF_TMAC_TOP_TCR2_RX_RIFS_MODE_SHFT                 30
#define BN0_WF_TMAC_TOP_TCR2_TXOP_BURST_STOP_ADDR              BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_TXOP_BURST_STOP_MASK              0x20000000                // TXOP_BURST_STOP[29]
#define BN0_WF_TMAC_TOP_TCR2_TXOP_BURST_STOP_SHFT              29
#define BN0_WF_TMAC_TOP_TCR2_TXOP_ABORT_OPT_ADDR               BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_TXOP_ABORT_OPT_MASK               0x10000000                // TXOP_ABORT_OPT[28]
#define BN0_WF_TMAC_TOP_TCR2_TXOP_ABORT_OPT_SHFT               28
#define BN0_WF_TMAC_TOP_TCR2_SGI_SIG_ALIGN_EN_ADDR             BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_SGI_SIG_ALIGN_EN_MASK             0x08000000                // SGI_SIG_ALIGN_EN[27]
#define BN0_WF_TMAC_TOP_TCR2_SGI_SIG_ALIGN_EN_SHFT             27
#define BN0_WF_TMAC_TOP_TCR2_Reserved_TCR2_0_ADDR              BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_Reserved_TCR2_0_MASK              0x07F00000                // Reserved_TCR2_0[26..20]
#define BN0_WF_TMAC_TOP_TCR2_Reserved_TCR2_0_SHFT              20
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_DIS_ADDR                  BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_DIS_MASK                  0x00080000                // SCH_DET_DIS[19]
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_DIS_SHFT                  19
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_PERIOD_ADDR               BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_PERIOD_MASK               0x00040000                // SCH_DET_PERIOD[18]
#define BN0_WF_TMAC_TOP_TCR2_SCH_DET_PERIOD_SHFT               18
#define BN0_WF_TMAC_TOP_TCR2_SCH_IDLE_SEL_ADDR                 BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_SCH_IDLE_SEL_MASK                 0x00030000                // SCH_IDLE_SEL[17..16]
#define BN0_WF_TMAC_TOP_TCR2_SCH_IDLE_SEL_SHFT                 16
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_DET_GUARD_TIME_ADDR       BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_DET_GUARD_TIME_MASK       0x0000F000                // PRE_RTS_DET_GUARD_TIME[15..12]
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_DET_GUARD_TIME_SHFT       12
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_SEC_IDLE_SEL_ADDR         BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_SEC_IDLE_SEL_MASK         0x00000C00                // PRE_RTS_SEC_IDLE_SEL[11..10]
#define BN0_WF_TMAC_TOP_TCR2_PRE_RTS_SEC_IDLE_SEL_SHFT         10
#define BN0_WF_TMAC_TOP_TCR2_PRERTS_DET_DIS_ADDR               BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_PRERTS_DET_DIS_MASK               0x00000200                // PRERTS_DET_DIS[9]
#define BN0_WF_TMAC_TOP_TCR2_PRERTS_DET_DIS_SHFT               9
#define BN0_WF_TMAC_TOP_TCR2_LDPC_OFST_EN_ADDR                 BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_LDPC_OFST_EN_MASK                 0x00000100                // LDPC_OFST_EN[8]
#define BN0_WF_TMAC_TOP_TCR2_LDPC_OFST_EN_SHFT                 8
#define BN0_WF_TMAC_TOP_TCR2_BKOF_SX_OPT_ADDR                  BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_BKOF_SX_OPT_MASK                  0x00000080                // BKOF_SX_OPT[7]
#define BN0_WF_TMAC_TOP_TCR2_BKOF_SX_OPT_SHFT                  7
#define BN0_WF_TMAC_TOP_TCR2_BKOF_APSOFF_OPT_ADDR              BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_BKOF_APSOFF_OPT_MASK              0x00000040                // BKOF_APSOFF_OPT[6]
#define BN0_WF_TMAC_TOP_TCR2_BKOF_APSOFF_OPT_SHFT              6
#define BN0_WF_TMAC_TOP_TCR2_MAX_PSDU_CHK_EN_ADDR              BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_MAX_PSDU_CHK_EN_MASK              0x00000020                // MAX_PSDU_CHK_EN[5]
#define BN0_WF_TMAC_TOP_TCR2_MAX_PSDU_CHK_EN_SHFT              5
#define BN0_WF_TMAC_TOP_TCR2_MAX_LG_LEN_CHK_EN_ADDR            BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_MAX_LG_LEN_CHK_EN_MASK            0x00000010                // MAX_LG_LEN_CHK_EN[4]
#define BN0_WF_TMAC_TOP_TCR2_MAX_LG_LEN_CHK_EN_SHFT            4
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TXOP_ADDR              BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TXOP_MASK              0x00000008                // EDCCA_STOP_TXOP[3]
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TXOP_SHFT              3
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TRIGR_ADDR             BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TRIGR_MASK             0x00000004                // EDCCA_STOP_TRIGR[2]
#define BN0_WF_TMAC_TOP_TCR2_EDCCA_STOP_TRIGR_SHFT             2
#define BN0_WF_TMAC_TOP_TCR2_HT_EXTLTF_ADDR                    BN0_WF_TMAC_TOP_TCR2_ADDR
#define BN0_WF_TMAC_TOP_TCR2_HT_EXTLTF_MASK                    0x00000003                // HT_EXTLTF[1..0]
#define BN0_WF_TMAC_TOP_TCR2_HT_EXTLTF_SHFT                    0

/* =====================================================================================

  ---ACTXOPLR4 (0x820E4000 + 0x60)---

    AC22LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC23LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC23LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR4_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC23LIMIT_MASK               0xFFFF0000                // AC23LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC23LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC22LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR4_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC22LIMIT_MASK               0x0000FFFF                // AC22LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR4_AC22LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR5 (0x820E4000 + 0x64)---

    AC20LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC21LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC21LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR5_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC21LIMIT_MASK               0xFFFF0000                // AC21LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC21LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC20LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR5_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC20LIMIT_MASK               0x0000FFFF                // AC20LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR5_AC20LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR6 (0x820E4000 + 0x68)---

    AC32LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC33LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC33LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR6_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC33LIMIT_MASK               0xFFFF0000                // AC33LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC33LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC32LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR6_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC32LIMIT_MASK               0x0000FFFF                // AC32LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR6_AC32LIMIT_SHFT               0

/* =====================================================================================

  ---ACTXOPLR7 (0x820E4000 + 0x6C)---

    AC30LIMIT[15..0]             - (RW) Same as defined in AC03Limit
    AC31LIMIT[31..16]            - (RW) Same as defined in AC03Limit

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC31LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR7_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC31LIMIT_MASK               0xFFFF0000                // AC31LIMIT[31..16]
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC31LIMIT_SHFT               16
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC30LIMIT_ADDR               BN0_WF_TMAC_TOP_ACTXOPLR7_ADDR
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC30LIMIT_MASK               0x0000FFFF                // AC30LIMIT[15..0]
#define BN0_WF_TMAC_TOP_ACTXOPLR7_AC30LIMIT_SHFT               0

/* =====================================================================================

  ---FP0R15 (0x820E4000 + 0x80)---

    VHT160_2_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    VHT160_3_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)
    VHT160_4_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    VHT160_5_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_5_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R15_ADDR
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_5_FRAME_POWER_DBM_MASK   0xFF000000                // VHT160_5_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_5_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_4_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R15_ADDR
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_4_FRAME_POWER_DBM_MASK   0x00FF0000                // VHT160_4_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_4_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_3_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R15_ADDR
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_3_FRAME_POWER_DBM_MASK   0x0000FF00                // VHT160_3_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_3_FRAME_POWER_DBM_SHFT   8
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_2_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R15_ADDR
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_2_FRAME_POWER_DBM_MASK   0x000000FF                // VHT160_2_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R15_VHT160_2_FRAME_POWER_DBM_SHFT   0

/* =====================================================================================

  ---FP0R16 (0x820E4000 + 0x84)---

    VHT160_6_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    VHT160_7_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)
    VHT160_8_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    VHT160_9_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_9_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R16_ADDR
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_9_FRAME_POWER_DBM_MASK   0xFF000000                // VHT160_9_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_9_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_8_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R16_ADDR
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_8_FRAME_POWER_DBM_MASK   0x00FF0000                // VHT160_8_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_8_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_7_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R16_ADDR
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_7_FRAME_POWER_DBM_MASK   0x0000FF00                // VHT160_7_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_7_FRAME_POWER_DBM_SHFT   8
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_6_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R16_ADDR
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_6_FRAME_POWER_DBM_MASK   0x000000FF                // VHT160_6_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R16_VHT160_6_FRAME_POWER_DBM_SHFT   0

/* =====================================================================================

  ---FP0R17 (0x820E4000 + 0x88)---

    LG_OFDM40__FRAME_POWER_OFFSET_DBM[7..0] - (RW) TX power of LG_OFDM40 is equal to TX power of LG_OFDM20 + LG_OFDM40 power offset.
    LG_OFDM80_FRAME_POWER_OFFSET_DBM[15..8] - (RW) TX power of LG_OFDM80 is equal to TX power of LG_OFDM20 + LG_OFDM80 power offset.
    LG_OFDM160_FRAME_POWER_OFFSET_DBM[23..16] - (RW) TX power of LG_OFDM 160 is equal to TX power of LG_OFDM20 + LG_OFDM160 power offset.
    HT40_8_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation MCS32 rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R17_HT40_8_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R17_ADDR
#define BN0_WF_TMAC_TOP_FP0R17_HT40_8_FRAME_POWER_DBM_MASK     0xFF000000                // HT40_8_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R17_HT40_8_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM160_FRAME_POWER_OFFSET_DBM_ADDR BN0_WF_TMAC_TOP_FP0R17_ADDR
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM160_FRAME_POWER_OFFSET_DBM_MASK 0x00FF0000                // LG_OFDM160_FRAME_POWER_OFFSET_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM160_FRAME_POWER_OFFSET_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM80_FRAME_POWER_OFFSET_DBM_ADDR BN0_WF_TMAC_TOP_FP0R17_ADDR
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM80_FRAME_POWER_OFFSET_DBM_MASK 0x0000FF00                // LG_OFDM80_FRAME_POWER_OFFSET_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM80_FRAME_POWER_OFFSET_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM40__FRAME_POWER_OFFSET_DBM_ADDR BN0_WF_TMAC_TOP_FP0R17_ADDR
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM40__FRAME_POWER_OFFSET_DBM_MASK 0x000000FF                // LG_OFDM40__FRAME_POWER_OFFSET_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R17_LG_OFDM40__FRAME_POWER_OFFSET_DBM_SHFT 0

/* =====================================================================================

  ---TRCR2 (0x820E4000 + 0x8C)---

    MNG_I2T_CHK[0]               - (RW) For Management Queues:
                                     Enables IDLE to TX CCA check
                                     1'b0: Disable to check if CCA/CCA_CS is busy at I2T_Chk_Point
                                     1'b1: Enable to check if CCA/CCA_CS is busy at I2T_Chk_Point
    MNG_BKOF_IGNORE_ED[1]        - (RW) For Management Queues:
                                     Ignores CCA_ED during backoff count-down.
                                     1'b0: CCA_ED will pause backoff count-down.
                                     2'b1: CCA_ED will not pause backoff count-down.
    MNG_CCA_SRC_SEL[3..2]        - (RW) For Management Queues:
                                     (CCA_ED | CCA_PLD | MDRDY) means high energy detected.
                                     CCA_CS means PPDU preamable detected.
                                     2'b00: (CCA_ED | CCA_PLD | MDRDY)
                                     2'b01: CCA_CS
                                     2'b10: (CCA_ED | CCA_PLD | MDRDY) | CCA_CS
                                     2'b11: (CCA_ED | CCA_PLD | MDRDY) & CCA_CS
    MNG_SLOT_IDLE_EN[4]          - (RW) Enables another Slot Idle Generation only for Management Queues (like Beacon)
    RESERVED5[31..5]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TRCR2_MNG_SLOT_IDLE_EN_ADDR            BN0_WF_TMAC_TOP_TRCR2_ADDR
#define BN0_WF_TMAC_TOP_TRCR2_MNG_SLOT_IDLE_EN_MASK            0x00000010                // MNG_SLOT_IDLE_EN[4]
#define BN0_WF_TMAC_TOP_TRCR2_MNG_SLOT_IDLE_EN_SHFT            4
#define BN0_WF_TMAC_TOP_TRCR2_MNG_CCA_SRC_SEL_ADDR             BN0_WF_TMAC_TOP_TRCR2_ADDR
#define BN0_WF_TMAC_TOP_TRCR2_MNG_CCA_SRC_SEL_MASK             0x0000000C                // MNG_CCA_SRC_SEL[3..2]
#define BN0_WF_TMAC_TOP_TRCR2_MNG_CCA_SRC_SEL_SHFT             2
#define BN0_WF_TMAC_TOP_TRCR2_MNG_BKOF_IGNORE_ED_ADDR          BN0_WF_TMAC_TOP_TRCR2_ADDR
#define BN0_WF_TMAC_TOP_TRCR2_MNG_BKOF_IGNORE_ED_MASK          0x00000002                // MNG_BKOF_IGNORE_ED[1]
#define BN0_WF_TMAC_TOP_TRCR2_MNG_BKOF_IGNORE_ED_SHFT          1
#define BN0_WF_TMAC_TOP_TRCR2_MNG_I2T_CHK_ADDR                 BN0_WF_TMAC_TOP_TRCR2_ADDR
#define BN0_WF_TMAC_TOP_TRCR2_MNG_I2T_CHK_MASK                 0x00000001                // MNG_I2T_CHK[0]
#define BN0_WF_TMAC_TOP_TRCR2_MNG_I2T_CHK_SHFT                 0

/* =====================================================================================

  ---CDTR (0x820E4000 + 0x90)---

    CCK_MDRDY_TOUT[15..0]        - (RW) CCK MDRDY response timeout time
                                     Timeout for an STA to wait for a CTS/ACK frame before concluding that the transmitted RTS/data frame failed This value is used for starting a timer since the end of the transmission of the frame for which the acknowledgement is required. If the baseband processor indicates that the successful PLCP header CRC checks a received frame before timer timeout, TMAC will stop and clear this timer then check whether the received frame is a CTS/ACK frame. Otherwise, TMAC will treat the frame transmission as being failed when the timer times out. This value can be set according to the worst case using long preamble. MT6620 should sample MDRDY at timeout time instead of clearing timer by MDRDY positive edge.
                                     Unit: 1us
                                     Note: This value is available when the expected RX rate is CCK rate.
    CCK_CCA_TOUT[31..16]         - (RW) CCK CCA response timeout time
                                     Timeout for an STA to wait for a CTS/ACK frame after transmitting an RTS/data frame
                                     This value is used for starting a timer since the end of the RTS/data frame transmission. If the baseband processor indicates CCA before timer timeout, TMAC will stop and clear this timer. Otherwise, TMAC will be treated as being failed when the timer times out. Chip should sample CCA at timeout time instead of clearing timer by CCA positive edge.
                                     Unit: 1us
                                     Note: This value is available when the expected RX rate is CCK rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_CDTR_CCK_CCA_TOUT_ADDR                 BN0_WF_TMAC_TOP_CDTR_ADDR
#define BN0_WF_TMAC_TOP_CDTR_CCK_CCA_TOUT_MASK                 0xFFFF0000                // CCK_CCA_TOUT[31..16]
#define BN0_WF_TMAC_TOP_CDTR_CCK_CCA_TOUT_SHFT                 16
#define BN0_WF_TMAC_TOP_CDTR_CCK_MDRDY_TOUT_ADDR               BN0_WF_TMAC_TOP_CDTR_ADDR
#define BN0_WF_TMAC_TOP_CDTR_CCK_MDRDY_TOUT_MASK               0x0000FFFF                // CCK_MDRDY_TOUT[15..0]
#define BN0_WF_TMAC_TOP_CDTR_CCK_MDRDY_TOUT_SHFT               0

/* =====================================================================================

  ---ODTR (0x820E4000 + 0x94)---

    OFDM_MDRDY_TOUT[15..0]       - (RW) OFDM MDRDY response timeout time
                                     Same as CCK_MDRDY_Timeout.
                                     Note: This value is available when the expected RX rate is OFDM rate.
    OFDM_CCA_TOUT[31..16]        - (RW) OFDM CCA response timeout time
                                     Same as CCK_CCA_Timeout.
                                     Note: This value is available when the expected RX rate is OFDM rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ODTR_OFDM_CCA_TOUT_ADDR                BN0_WF_TMAC_TOP_ODTR_ADDR
#define BN0_WF_TMAC_TOP_ODTR_OFDM_CCA_TOUT_MASK                0xFFFF0000                // OFDM_CCA_TOUT[31..16]
#define BN0_WF_TMAC_TOP_ODTR_OFDM_CCA_TOUT_SHFT                16
#define BN0_WF_TMAC_TOP_ODTR_OFDM_MDRDY_TOUT_ADDR              BN0_WF_TMAC_TOP_ODTR_ADDR
#define BN0_WF_TMAC_TOP_ODTR_OFDM_MDRDY_TOUT_MASK              0x0000FFFF                // OFDM_MDRDY_TOUT[15..0]
#define BN0_WF_TMAC_TOP_ODTR_OFDM_MDRDY_TOUT_SHFT              0

/* =====================================================================================

  ---ATCR (0x820E4000 + 0x98)---

    TXV_TOUT[7..0]               - (RW) TX vector timeout time
                                     Timeout value for TMAC to prepare the first TX vector 
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    RIFS_TXV_TOUT[15..8]         - (RW) RIFS TX vector timeout time
                                     Timeout value for TMAC to prepare the first TX vector for TX RIFS frame
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    AGG_TOUT[24..16]             - (RW) Aggregation timeout time
                                     Timeout value for aggregation to finish the aggregation process 
                                     802.11abgn mode: 9us (NC)
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled. (ARB.SCR.MAC_TX_DIS)
    RESERVED25[31..25]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ATCR_AGG_TOUT_ADDR                     BN0_WF_TMAC_TOP_ATCR_ADDR
#define BN0_WF_TMAC_TOP_ATCR_AGG_TOUT_MASK                     0x01FF0000                // AGG_TOUT[24..16]
#define BN0_WF_TMAC_TOP_ATCR_AGG_TOUT_SHFT                     16
#define BN0_WF_TMAC_TOP_ATCR_RIFS_TXV_TOUT_ADDR                BN0_WF_TMAC_TOP_ATCR_ADDR
#define BN0_WF_TMAC_TOP_ATCR_RIFS_TXV_TOUT_MASK                0x0000FF00                // RIFS_TXV_TOUT[15..8]
#define BN0_WF_TMAC_TOP_ATCR_RIFS_TXV_TOUT_SHFT                8
#define BN0_WF_TMAC_TOP_ATCR_TXV_TOUT_ADDR                     BN0_WF_TMAC_TOP_ATCR_ADDR
#define BN0_WF_TMAC_TOP_ATCR_TXV_TOUT_MASK                     0x000000FF                // TXV_TOUT[7..0]
#define BN0_WF_TMAC_TOP_ATCR_TXV_TOUT_SHFT                     0

/* =====================================================================================

  ---TRCR0 (0x820E4000 + 0x9C)---

    TR2T_CHK[8..0]               - (RW) Duration of R2T and T2T check point 
                                     802.11abgn mode: 7us (NC)
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode) 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)v
    RIFS_T2T_CHK[15..9]          - (RW) Duration of T2T check point for TX RIFS frame
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode) 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    I2T_CHK[24..16]              - (RW) Duration of I2T_Chk
                                     Suggested values for configuration:
                                     802.11abgn mode: Long slot time: 17us (NC)
                                     802.11abgn mode: Short slot time: 6us (NC)
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode) 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    I2T_CHK_EN[25]               - (RW) Enables IDLE to TX CCA check
                                     1'b0: Disable to check if CCA/CCA_CS is busy at I2T_Chk_Point
                                     1'b1: Enable to check if CCA/CCA_CS is busy at I2T_Chk_Point
    I2T_CHK_SCH_EN[26]           - (RW) Enables IDLE to TX SEC_CCA check
                                     1'b0: Disable to check if CCA_SEC is busy at I2T_CHK_POINT
                                     1'b1: Enable to check if CCA_SEC is busy at I2T_CHK_POINT
    BKOF_IGNORE_ED[27]           - (RW) Ignores CCA_ED during backoff count-down
                                     1'b0: CCA_ED will pause backoff count down.
                                     1'b1: CCA_ED will not pause backoff count down.
    CCA_SEC_SRC_SEL[29..28]      - (RW) Selects second channel CCA mode
                                     There are two CCA signals, CCA_SEC and CCA_SEC_CS.
                                     CCA_SEC means high energy detected.
                                     CCA_SEC_CS means PPDU preamable detected.
                                     2'b00: CCA_SEC
                                     2'b01: CCA_SEC_CS
                                     2'b10: CCA_SEC | CCA_SEC_CS
                                     2'b11: CCA_SEC & CCA_SEC_CS
                                     Note: This setting can be applied to SEC20/40/80.
    CCA_SRC_SEL[31..30]          - (RW) Selects primary channel CCA mode
                                     There are two CCA signals, (CCA_ED | CCA_PLD| MDRDY) and CCA_CS.
                                     (CCA_ED | CCA_PLD | MDRDY) means high energy detected.
                                     CCA_CS means PPDU preamable detected.
                                     2'b00: (CCA_ED | CCA_PLD | MDRDY)
                                     2'b01: CCA_CS
                                     2'b10: (CCA_ED | CCA_PLD | MDRDY) | CCA_CS
                                     2'b11: (CCA_ED | CCA_PLD | MDRDY) & CCA_CS

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SRC_SEL_ADDR                 BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SRC_SEL_MASK                 0xC0000000                // CCA_SRC_SEL[31..30]
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SRC_SEL_SHFT                 30
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SEC_SRC_SEL_ADDR             BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SEC_SRC_SEL_MASK             0x30000000                // CCA_SEC_SRC_SEL[29..28]
#define BN0_WF_TMAC_TOP_TRCR0_CCA_SEC_SRC_SEL_SHFT             28
#define BN0_WF_TMAC_TOP_TRCR0_BKOF_IGNORE_ED_ADDR              BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_BKOF_IGNORE_ED_MASK              0x08000000                // BKOF_IGNORE_ED[27]
#define BN0_WF_TMAC_TOP_TRCR0_BKOF_IGNORE_ED_SHFT              27
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_SCH_EN_ADDR              BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_SCH_EN_MASK              0x04000000                // I2T_CHK_SCH_EN[26]
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_SCH_EN_SHFT              26
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_EN_ADDR                  BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_EN_MASK                  0x02000000                // I2T_CHK_EN[25]
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_EN_SHFT                  25
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_ADDR                     BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_MASK                     0x01FF0000                // I2T_CHK[24..16]
#define BN0_WF_TMAC_TOP_TRCR0_I2T_CHK_SHFT                     16
#define BN0_WF_TMAC_TOP_TRCR0_RIFS_T2T_CHK_ADDR                BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_RIFS_T2T_CHK_MASK                0x0000FE00                // RIFS_T2T_CHK[15..9]
#define BN0_WF_TMAC_TOP_TRCR0_RIFS_T2T_CHK_SHFT                9
#define BN0_WF_TMAC_TOP_TRCR0_TR2T_CHK_ADDR                    BN0_WF_TMAC_TOP_TRCR0_ADDR
#define BN0_WF_TMAC_TOP_TRCR0_TR2T_CHK_MASK                    0x000001FF                // TR2T_CHK[8..0]
#define BN0_WF_TMAC_TOP_TRCR0_TR2T_CHK_SHFT                    0

/* =====================================================================================

  ---RRCR (0x820E4000 + 0xA0)---

    RXREQ_DLY[8..0]              - (RW) Delay time of MAC RX ON
                                     Unit: 50ns/100ns/200ns (NC/HC/QC mode) 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_RX_DIS)
    RESERVED9[31..9]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_RRCR_RXREQ_DLY_ADDR                    BN0_WF_TMAC_TOP_RRCR_ADDR
#define BN0_WF_TMAC_TOP_RRCR_RXREQ_DLY_MASK                    0x000001FF                // RXREQ_DLY[8..0]
#define BN0_WF_TMAC_TOP_RRCR_RXREQ_DLY_SHFT                    0

/* =====================================================================================

  ---ICR0 (0x820E4000 + 0xA4)---

    EIFS_TIME[8..0]              - (RW) EIFS time minus DIFS
                                     Unit: 1us
                                     Note: The inaccuracy is around 1 ~ 11us.
    RESERVED9[9]                 - (RO) Reserved bits
    RIFS_TIME[14..10]            - (RW) RIFS time
                                     Unit: 1us 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    RESERVED15[15]               - (RO) Reserved bits
    SIFS_TIME[22..16]            - (RW) SIFS time
                                     Unit: 1us 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    SIFS_START_IGNORE_NAV[23]    - (RW) SIFS start depeonds on NAV = 0 or not, 1'b0: start when NAV=0, 1'b1: ignore NAV and start
    SLOT_TIME[30..24]            - (RW) Slot time
                                     Unit: 1us 
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_ICR0_SLOT_TIME_ADDR                    BN0_WF_TMAC_TOP_ICR0_ADDR
#define BN0_WF_TMAC_TOP_ICR0_SLOT_TIME_MASK                    0x7F000000                // SLOT_TIME[30..24]
#define BN0_WF_TMAC_TOP_ICR0_SLOT_TIME_SHFT                    24
#define BN0_WF_TMAC_TOP_ICR0_SIFS_START_IGNORE_NAV_ADDR        BN0_WF_TMAC_TOP_ICR0_ADDR
#define BN0_WF_TMAC_TOP_ICR0_SIFS_START_IGNORE_NAV_MASK        0x00800000                // SIFS_START_IGNORE_NAV[23]
#define BN0_WF_TMAC_TOP_ICR0_SIFS_START_IGNORE_NAV_SHFT        23
#define BN0_WF_TMAC_TOP_ICR0_SIFS_TIME_ADDR                    BN0_WF_TMAC_TOP_ICR0_ADDR
#define BN0_WF_TMAC_TOP_ICR0_SIFS_TIME_MASK                    0x007F0000                // SIFS_TIME[22..16]
#define BN0_WF_TMAC_TOP_ICR0_SIFS_TIME_SHFT                    16
#define BN0_WF_TMAC_TOP_ICR0_RIFS_TIME_ADDR                    BN0_WF_TMAC_TOP_ICR0_ADDR
#define BN0_WF_TMAC_TOP_ICR0_RIFS_TIME_MASK                    0x00007C00                // RIFS_TIME[14..10]
#define BN0_WF_TMAC_TOP_ICR0_RIFS_TIME_SHFT                    10
#define BN0_WF_TMAC_TOP_ICR0_EIFS_TIME_ADDR                    BN0_WF_TMAC_TOP_ICR0_ADDR
#define BN0_WF_TMAC_TOP_ICR0_EIFS_TIME_MASK                    0x000001FF                // EIFS_TIME[8..0]
#define BN0_WF_TMAC_TOP_ICR0_EIFS_TIME_SHFT                    0

/* =====================================================================================

  ---PPDR (0x820E4000 + 0xA8)---

    DDLMT_DLY_OFST_HT[7..0]      - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_VHT[15..8]    - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    RESERVED16[19..16]           - (RO) Reserved bits
    PHY_DLY[23..20]              - (RW) PHY TX delay
                                     Unit: 1us
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_PPDR_PHY_DLY_ADDR                      BN0_WF_TMAC_TOP_PPDR_ADDR
#define BN0_WF_TMAC_TOP_PPDR_PHY_DLY_MASK                      0x00F00000                // PHY_DLY[23..20]
#define BN0_WF_TMAC_TOP_PPDR_PHY_DLY_SHFT                      20
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_VHT_ADDR           BN0_WF_TMAC_TOP_PPDR_ADDR
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_VHT_MASK           0x0000FF00                // DDLMT_DLY_OFST_VHT[15..8]
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_VHT_SHFT           8
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_HT_ADDR            BN0_WF_TMAC_TOP_PPDR_ADDR
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_HT_MASK            0x000000FF                // DDLMT_DLY_OFST_HT[7..0]
#define BN0_WF_TMAC_TOP_PPDR_DDLMT_DLY_OFST_HT_SHFT            0

/* =====================================================================================

  ---BCSR (0x820E4000 + 0xAC)---

    USEC_CCNT[8..0]              - (RW) Defines "1us" is equal to how many "WIFI MAC 1x clock" cycles
    RESERVED9[15..9]             - (RO) Reserved bits
    BCK_CCNT[20..16]             - (RW) Defines "basic clock" is euqla to how many "WIFI MAC 1x clock" cycles
                                     Note: The period of "basic clock" is 50ns/100ns/200ns (NC/HC/QC mode).
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BCSR_BCK_CCNT_ADDR                     BN0_WF_TMAC_TOP_BCSR_ADDR
#define BN0_WF_TMAC_TOP_BCSR_BCK_CCNT_MASK                     0x001F0000                // BCK_CCNT[20..16]
#define BN0_WF_TMAC_TOP_BCSR_BCK_CCNT_SHFT                     16
#define BN0_WF_TMAC_TOP_BCSR_USEC_CCNT_ADDR                    BN0_WF_TMAC_TOP_BCSR_ADDR
#define BN0_WF_TMAC_TOP_BCSR_USEC_CCNT_MASK                    0x000001FF                // USEC_CCNT[8..0]
#define BN0_WF_TMAC_TOP_BCSR_USEC_CCNT_SHFT                    0

/* =====================================================================================

  ---BRCR0 (0x820E4000 + 0xB0)---

    BFEE_RATE[12..0]             - (RW) TX rate for beamform report frame
                                     Bit[12:10]: Nsts: Count of space time stream
                                     3'b000: Nsts = 1
                                     3'b001: Nsts = 2
                                     3'b010: Nsts = 3
                                     3'b011: Nsts = 4
                                     3'b100: Nsts = 5
                                     3'b101: Nsts = 6
                                     3'b110: Nsts = 7
                                     3'b111: Nsts = 8
                                     Bit[9:6]: TX mode
                                     Indicates the transmission mode
                                     4'b0000: Legacy CCK
                                     4'b0001: Legacy OFDM
                                     4'b0010: HT mixed mode
                                     4'b0011: HT green field mode
                                     4'b0100: VHT mode
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     For HT rate:
                                     Bit 0~5 indicate MCSN, N=0~23 and 32, others reserved.
                                     For VHT rate:
                                     Bit 0~5 indicate MCSN, N=0~9, others reserved.
                                     For HE rate:
                                     Bit 0~4 indicate MCSN, N=)~``, other reserved
                                     Bit4 indicate HE DCM
                                     bit5 indicate HE_ER_SU 106Tone
    BFEE_STBC_EN[13]             - (RW) Enables STBC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/VHT only)
    BFEE_LDPC_EN[14]             - (RW) Enables LDPC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/VHT only)
    BFEE_DOPPLER[15]             - (RW) Doppler Enable
                                     1'b0: Disable
                                     1'b1: Enable (HE only)
    BFEE_PE[17..16]              - (RW) Max. PE for BF Report frame
                                     00: 0us
                                     01:8us
                                     10: 16us
                                     11: reserved
    RESERVED18[23..18]           - (RO) Reserved bits
    BFEE_GI_TYPE[25..24]         - (RW) GI Type
                                     HT/VHT
                                     2'b0: Normal GI
                                     2'b1: Short GI
                                     others: reserved
                                     HE:
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI
                                     others: reserved
    BFEE_HELTF_TYPE[27..26]      - (RW) indicate HE_LTF_TYPE
                                     2'h0: x1 LTF (3.2us)
                                     2'h1: x2 LTF (6.4us)
                                     2'h2: x4 LTF (12.8us)
                                     others: reserved
    BFEE_FIX_BW[29..28]          - (RW) TX bandwidth for beamform report frame
                                     2'b00: 20M BW
                                     2'b01: 40M BW
                                     2'b10: 80M BW
                                     2'b11: 160M BW/80+80M BW
    RESERVED30[30]               - (RO) Reserved bits
    BFEE_BW_SEL[31]              - (RW) Selects BW
                                     1'b0: Same as NDPA/NDP BW
                                     1'b1: Use fixed BW

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_BW_SEL_ADDR                 BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_BW_SEL_MASK                 0x80000000                // BFEE_BW_SEL[31]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_BW_SEL_SHFT                 31
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_FIX_BW_ADDR                 BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_FIX_BW_MASK                 0x30000000                // BFEE_FIX_BW[29..28]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_FIX_BW_SHFT                 28
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_HELTF_TYPE_ADDR             BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_HELTF_TYPE_MASK             0x0C000000                // BFEE_HELTF_TYPE[27..26]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_HELTF_TYPE_SHFT             26
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_GI_TYPE_ADDR                BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_GI_TYPE_MASK                0x03000000                // BFEE_GI_TYPE[25..24]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_GI_TYPE_SHFT                24
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_PE_ADDR                     BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_PE_MASK                     0x00030000                // BFEE_PE[17..16]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_PE_SHFT                     16
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_DOPPLER_ADDR                BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_DOPPLER_MASK                0x00008000                // BFEE_DOPPLER[15]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_DOPPLER_SHFT                15
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_LDPC_EN_ADDR                BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_LDPC_EN_MASK                0x00004000                // BFEE_LDPC_EN[14]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_LDPC_EN_SHFT                14
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_STBC_EN_ADDR                BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_STBC_EN_MASK                0x00002000                // BFEE_STBC_EN[13]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_STBC_EN_SHFT                13
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_RATE_ADDR                   BN0_WF_TMAC_TOP_BRCR0_ADDR
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_RATE_MASK                   0x00001FFF                // BFEE_RATE[12..0]
#define BN0_WF_TMAC_TOP_BRCR0_BFEE_RATE_SHFT                   0

/* =====================================================================================

  ---BRCR1 (0x820E4000 + 0xB8)---

    BFEE_ANT_ID[11..0]           - (RW) Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BFEE_SPE_IDX[28..24]         - (RW) Spatial expansion table index for beamform report frame
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_SPE_IDX_ADDR                BN0_WF_TMAC_TOP_BRCR1_ADDR
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_SPE_IDX_MASK                0x1F000000                // BFEE_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_SPE_IDX_SHFT                24
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_ANT_ID_ADDR                 BN0_WF_TMAC_TOP_BRCR1_ADDR
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_ANT_ID_MASK                 0x00000FFF                // BFEE_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_BRCR1_BFEE_ANT_ID_SHFT                 0

/* =====================================================================================

  ---B0BRR0 (0x820E4000 + 0xC0)---

    BSSID00_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    BSSID00_ACK_RATE_OPT[14..12] - (RW) Restrict the maximum response rate for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA)
                                     3'b0xx: no restriction
                                     3'b100: restrict to the lower 1 rate than RX rate
                                     3'b101: restrict to the lower 2 rates than RX rate
                                     3'b110: restrict to the lower 4 rates than RX rate
                                     3'b111: restrict to the lowest rate
    BSSID00_ACK_BW_OPT[15]       - (RW) Restrict the maximum response BW for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA)
                                     0: no restriction
                                     1: restrict to 20MHz
    BSSID00_SU_ACK_PE[17..16]    - (RW) Max. PE for SU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    BSSID00_MU_ACK_PE[19..18]    - (RW) Max. PE for MU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    RESERVED20[23..20]           - (RO) Reserved bits
    Reserved_B0BRR0_0[24]        - (RW) Reserved
    BSSID00_SW_RESP_RATE[27..25] - (RW) Software response rate (CCK only) for BSSID00/BSSID1x/BSSID2x
                                     CCK long preamble:
                                     3'b000: 1M
                                     3'b001: 2M
                                     3'b010: 5.5M
                                     3'b011: 11M
                                     CCK short preamble:
                                     3'b101: 2M
                                     3'b110: 5.5M
                                     3'b111: 11M
    BSSID00_SW_RESP_RATE_THRESHOLD[29..28] - (RW) Software response rate threshold for BSSID00/BSSID1x/BSSID2x
                                     2'b00: OFDM 6M
                                     2'b01: OFDM 9M
                                     2'b10: OFDM 12M
                                     2'b11: OFDM 18M
                                     If the original response rate is equal to or less than the threshold rate, the software response will be selected.
                                     (for Non-HT response rate only)
    RESERVED30[30]               - (RO) Reserved bits
    BSSID00_SW_RESP_RATE_EN[31]  - (RW) Enables software response rate for BSSID00/BSSID1x/BSSID2x
                                     1'b0: Disable
                                     1'b1: Enable

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_EN_ADDR    BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_EN_MASK    0x80000000                // BSSID00_SW_RESP_RATE_EN[31]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_EN_SHFT    31
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_THRESHOLD_ADDR BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_THRESHOLD_MASK 0x30000000                // BSSID00_SW_RESP_RATE_THRESHOLD[29..28]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_THRESHOLD_SHFT 28
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_ADDR       BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_MASK       0x0E000000                // BSSID00_SW_RESP_RATE[27..25]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SW_RESP_RATE_SHFT       25
#define BN0_WF_TMAC_TOP_B0BRR0_Reserved_B0BRR0_0_ADDR          BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_Reserved_B0BRR0_0_MASK          0x01000000                // Reserved_B0BRR0_0[24]
#define BN0_WF_TMAC_TOP_B0BRR0_Reserved_B0BRR0_0_SHFT          24
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_MU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_MU_ACK_PE_MASK          0x000C0000                // BSSID00_MU_ACK_PE[19..18]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_MU_ACK_PE_SHFT          18
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SU_ACK_PE_MASK          0x00030000                // BSSID00_SU_ACK_PE[17..16]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_SU_ACK_PE_SHFT          16
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_BW_OPT_ADDR         BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_BW_OPT_MASK         0x00008000                // BSSID00_ACK_BW_OPT[15]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_BW_OPT_SHFT         15
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_RATE_OPT_ADDR       BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_RATE_OPT_MASK       0x00007000                // BSSID00_ACK_RATE_OPT[14..12]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_ACK_RATE_OPT_SHFT       12
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_LG_RATE_MAP_ADDR        BN0_WF_TMAC_TOP_B0BRR0_ADDR
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_LG_RATE_MAP_MASK        0x00000FFF                // BSSID00_LG_RATE_MAP[11..0]
#define BN0_WF_TMAC_TOP_B0BRR0_BSSID00_LG_RATE_MAP_SHFT        0

/* =====================================================================================

  ---B0BRR1 (0x820E4000 + 0xC4)---

    BSSID00_RESP_ANT_ID[11..0]   - (RW) Global ANT_ID setting for BSSID00/BSSID1x/BSSID2x response frame
                                     Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BSSID00_SPE_IDX[28..24]      - (RW) Spatial expansion table index for BSSID00/BSSID1x/BSSID2x
                                     (ACK/BA/CTS)
    RESERVED29[30..29]           - (RO) Reserved bits
    BSSID00_RESP_ANT_ID_SEL[31]  - (RW) Response ANT_ID mode for BSSID00/BSSID1x/BSSID2x
                                     1'b0: Select global response ANT_ID setting
                                     1'b1: Follow the peer's optimal TX ANT_ID (in WTBL)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_SEL_ADDR    BN0_WF_TMAC_TOP_B0BRR1_ADDR
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_SEL_MASK    0x80000000                // BSSID00_RESP_ANT_ID_SEL[31]
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_SEL_SHFT    31
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_SPE_IDX_ADDR            BN0_WF_TMAC_TOP_B0BRR1_ADDR
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_SPE_IDX_MASK            0x1F000000                // BSSID00_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_SPE_IDX_SHFT            24
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_ADDR        BN0_WF_TMAC_TOP_B0BRR1_ADDR
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_MASK        0x00000FFF                // BSSID00_RESP_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_B0BRR1_BSSID00_RESP_ANT_ID_SHFT        0

/* =====================================================================================

  ---B1BRR0 (0x820E4000 + 0xC8)---

    BSSID01_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID01 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    BSSID01_ACK_RATE_OPT[14..12] - (RW) Restrict the maximum response rate for BSSID01 (ACK/BA/MTBA)
                                     3'b0xx: no restriction
                                     3'b100: restrict to the lower 1 rate than RX rate
                                     3'b101: restrict to the lower 2 rates than RX rate
                                     3'b110: restrict to the lower 4 rates than RX rate
                                     3'b111: restrict to the lowest rate
    BSSID01_ACK_BW_OPT[15]       - (RW) Restrict the maximum response BW for BSSID01 (ACK/BA/MTBA)
                                     0: no restriction
                                     1: restrict to 20MHz
    BSSID01_SU_ACK_PE[17..16]    - (RW) Max. PE for SU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    BSSID01_MU_ACK_PE[19..18]    - (RW) Max. PE for MU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    RESERVED20[23..20]           - (RO) Reserved bits
    Reserved_B1BRR0_0[24]        - (RW) Reserved
    BSSID01_SW_RESP_RATE[27..25] - (RW) Software response rate (CCK only) for BSSID01
                                     CCK long preamble:
                                     3'b000: 1M
                                     3'b001: 2M
                                     3'b010: 5.5M
                                     3'b011: 11M
                                     CCK short preamble:
                                     3'b101: 2M
                                     3'b110: 5.5M
                                     3'b111: 11M
    BSSID01_SW_RESP_RATE_THRESHOLD[29..28] - (RW) Software response rate threshold for BSSID01
                                     2'b00: OFDM 6M
                                     2'b01: OFDM 9M
                                     2'b10: OFDM 12M
                                     2'b11: OFDM 18M
                                     If the original response rate is equal to or less than the threshold rate, the software response will be selected.
                                     (for Non-HT response rate only)
    RESERVED30[30]               - (RO) Reserved bits
    BSSID01_SW_RESP_RATE_EN[31]  - (RW) Enables software response rate for BSSID01
                                     1'b0: Disable
                                     1'b1: Enable

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_EN_ADDR    BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_EN_MASK    0x80000000                // BSSID01_SW_RESP_RATE_EN[31]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_EN_SHFT    31
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_THRESHOLD_ADDR BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_THRESHOLD_MASK 0x30000000                // BSSID01_SW_RESP_RATE_THRESHOLD[29..28]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_THRESHOLD_SHFT 28
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_ADDR       BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_MASK       0x0E000000                // BSSID01_SW_RESP_RATE[27..25]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SW_RESP_RATE_SHFT       25
#define BN0_WF_TMAC_TOP_B1BRR0_Reserved_B1BRR0_0_ADDR          BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_Reserved_B1BRR0_0_MASK          0x01000000                // Reserved_B1BRR0_0[24]
#define BN0_WF_TMAC_TOP_B1BRR0_Reserved_B1BRR0_0_SHFT          24
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_MU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_MU_ACK_PE_MASK          0x000C0000                // BSSID01_MU_ACK_PE[19..18]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_MU_ACK_PE_SHFT          18
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SU_ACK_PE_MASK          0x00030000                // BSSID01_SU_ACK_PE[17..16]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_SU_ACK_PE_SHFT          16
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_BW_OPT_ADDR         BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_BW_OPT_MASK         0x00008000                // BSSID01_ACK_BW_OPT[15]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_BW_OPT_SHFT         15
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_RATE_OPT_ADDR       BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_RATE_OPT_MASK       0x00007000                // BSSID01_ACK_RATE_OPT[14..12]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_ACK_RATE_OPT_SHFT       12
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_LG_RATE_MAP_ADDR        BN0_WF_TMAC_TOP_B1BRR0_ADDR
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_LG_RATE_MAP_MASK        0x00000FFF                // BSSID01_LG_RATE_MAP[11..0]
#define BN0_WF_TMAC_TOP_B1BRR0_BSSID01_LG_RATE_MAP_SHFT        0

/* =====================================================================================

  ---B1BRR1 (0x820E4000 + 0xCC)---

    BSSID01_RESP_ANT_ID[11..0]   - (RW) Global ANT_ID setting for BSSID01 response frame
                                     Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BSSID01_SPE_IDX[28..24]      - (RW) Spatial expansion table index for BSSID01
                                     (ACK/BA/CTS)
    RESERVED29[30..29]           - (RO) Reserved bits
    BSSID01_RESP_ANT_ID_SEL[31]  - (RW) Response ANT_ID mode for BSSID01
                                     1'b0: Select global response ANT_ID setting
                                     1'b1: Follow the peer's optimal TX ANT_ID (in WTBL)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_SEL_ADDR    BN0_WF_TMAC_TOP_B1BRR1_ADDR
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_SEL_MASK    0x80000000                // BSSID01_RESP_ANT_ID_SEL[31]
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_SEL_SHFT    31
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_SPE_IDX_ADDR            BN0_WF_TMAC_TOP_B1BRR1_ADDR
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_SPE_IDX_MASK            0x1F000000                // BSSID01_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_SPE_IDX_SHFT            24
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_ADDR        BN0_WF_TMAC_TOP_B1BRR1_ADDR
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_MASK        0x00000FFF                // BSSID01_RESP_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_B1BRR1_BSSID01_RESP_ANT_ID_SHFT        0

/* =====================================================================================

  ---B2BRR0 (0x820E4000 + 0xD0)---

    BSSID02_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID02 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    BSSID02_ACK_RATE_OPT[14..12] - (RW) Restrict the maximum response rate for BSSID02 (ACK/BA/MTBA)
                                     3'b0xx: no restriction
                                     3'b100: restrict to the lower 1 rate than RX rate
                                     3'b101: restrict to the lower 2 rates than RX rate
                                     3'b110: restrict to the lower 4 rates than RX rate
                                     3'b111: restrict to the lowest rate
    BSSID02_ACK_BW_OPT[15]       - (RW) Restrict the maximum response BW for BSSID02 (ACK/BA/MTBA)
                                     0: no restriction
                                     1: restrict to 20MHz
    BSSID02_SU_ACK_PE[17..16]    - (RW) Max. PE for SU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    BSSID02_MU_ACK_PE[19..18]    - (RW) Max. PE for MU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    RESERVED20[23..20]           - (RO) Reserved bits
    Reserved_B2BRR0_0[24]        - (RW) Reserved
    BSSID02_SW_RESP_RATE[27..25] - (RW) Software response rate (CCK only) for BSSID02
                                     CCK long preamble:
                                     3'b000: 1M
                                     3'b001: 2M
                                     3'b010: 5.5M
                                     3'b011: 11M
                                     CCK short preamble:
                                     3'b101: 2M
                                     3'b110: 5.5M
                                     3'b111: 11M
    BSSID02_SW_RESP_RATE_THRESHOLD[29..28] - (RW) Software response rate threshold for BSSID02
                                     2'b00: OFDM 6M
                                     2'b01: OFDM 9M
                                     2'b10: OFDM 12M
                                     2'b11: OFDM 18M
                                     If the original response rate is equal to or less than the threshold rate, the software response will be selected.
                                     (for Non-HT response rate only)
    RESERVED30[30]               - (RO) Reserved bits
    BSSID02_SW_RESP_RATE_EN[31]  - (RW) Enables software response rate for BSSID02
                                     1'b0: Disable
                                     1'b1: Enable

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_EN_ADDR    BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_EN_MASK    0x80000000                // BSSID02_SW_RESP_RATE_EN[31]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_EN_SHFT    31
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_THRESHOLD_ADDR BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_THRESHOLD_MASK 0x30000000                // BSSID02_SW_RESP_RATE_THRESHOLD[29..28]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_THRESHOLD_SHFT 28
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_ADDR       BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_MASK       0x0E000000                // BSSID02_SW_RESP_RATE[27..25]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SW_RESP_RATE_SHFT       25
#define BN0_WF_TMAC_TOP_B2BRR0_Reserved_B2BRR0_0_ADDR          BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_Reserved_B2BRR0_0_MASK          0x01000000                // Reserved_B2BRR0_0[24]
#define BN0_WF_TMAC_TOP_B2BRR0_Reserved_B2BRR0_0_SHFT          24
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_MU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_MU_ACK_PE_MASK          0x000C0000                // BSSID02_MU_ACK_PE[19..18]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_MU_ACK_PE_SHFT          18
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SU_ACK_PE_MASK          0x00030000                // BSSID02_SU_ACK_PE[17..16]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_SU_ACK_PE_SHFT          16
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_BW_OPT_ADDR         BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_BW_OPT_MASK         0x00008000                // BSSID02_ACK_BW_OPT[15]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_BW_OPT_SHFT         15
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_RATE_OPT_ADDR       BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_RATE_OPT_MASK       0x00007000                // BSSID02_ACK_RATE_OPT[14..12]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_ACK_RATE_OPT_SHFT       12
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_LG_RATE_MAP_ADDR        BN0_WF_TMAC_TOP_B2BRR0_ADDR
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_LG_RATE_MAP_MASK        0x00000FFF                // BSSID02_LG_RATE_MAP[11..0]
#define BN0_WF_TMAC_TOP_B2BRR0_BSSID02_LG_RATE_MAP_SHFT        0

/* =====================================================================================

  ---B2BRR1 (0x820E4000 + 0xD4)---

    BSSID02_RESP_ANT_ID[11..0]   - (RW) Global ANT_ID setting for BSSID02 response frame
                                     Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BSSID02_SPE_IDX[28..24]      - (RW) Spatial expansion table index for BSSID02
                                     (ACK/BA/CTS)
    RESERVED29[30..29]           - (RO) Reserved bits
    BSSID02_RESP_ANT_ID_SEL[31]  - (RW) Response ANT_ID mode for BSSID02
                                     1'b0: Select global response ANT_ID setting
                                     1'b1: Follow the peer's optimal TX ANT_ID (in WTBL)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_SEL_ADDR    BN0_WF_TMAC_TOP_B2BRR1_ADDR
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_SEL_MASK    0x80000000                // BSSID02_RESP_ANT_ID_SEL[31]
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_SEL_SHFT    31
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_SPE_IDX_ADDR            BN0_WF_TMAC_TOP_B2BRR1_ADDR
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_SPE_IDX_MASK            0x1F000000                // BSSID02_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_SPE_IDX_SHFT            24
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_ADDR        BN0_WF_TMAC_TOP_B2BRR1_ADDR
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_MASK        0x00000FFF                // BSSID02_RESP_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_B2BRR1_BSSID02_RESP_ANT_ID_SHFT        0

/* =====================================================================================

  ---B3BRR0 (0x820E4000 + 0xD8)---

    BSSID03_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID03 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    BSSID03_ACK_RATE_OPT[14..12] - (RW) Restrict the maximum response rate for BSSID03 (ACK/BA/MTBA)
                                     3'b0xx: no restriction
                                     3'b100: restrict to the lower 1 rate than RX rate
                                     3'b101: restrict to the lower 2 rates than RX rate
                                     3'b110: restrict to the lower 4 rates than RX rate
                                     3'b111: restrict to the lowest rate
    BSSID03_ACK_BW_OPT[15]       - (RW) Restrict the maximum response BW for BSSID03 (ACK/BA/MTBA)
                                     0: no restriction
                                     1: restrict to 20MHz
    BSSID03_SU_ACK_PE[17..16]    - (RW) Max. PE for SU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    BSSID03_MU_ACK_PE[19..18]    - (RW) Max. PE for MU response
                                     00: 0us
                                     01: 8us
                                     10: 16us
    RESERVED20[23..20]           - (RO) Reserved bits
    Reserved_B3BRR0_0[24]        - (RW) Reserved
    BSSID03_SW_RESP_RATE[27..25] - (RW) Software response rate (CCK only) for BSSID03
                                     CCK long preamble:
                                     3'b000: 1M
                                     3'b001: 2M
                                     3'b010: 5.5M
                                     3'b011: 11M
                                     CCK short preamble:
                                     3'b101: 2M
                                     3'b110: 5.5M
                                     3'b111: 11M
    BSSID03_SW_RESP_RATE_THRESHOLD[29..28] - (RW) Software response rate threshold for BSSID03
                                     2'b00: OFDM 6M
                                     2'b01: OFDM 9M
                                     2'b10: OFDM 12M
                                     2'b11: OFDM 18M
                                     If the original response rate is equal to or less than the threshold rate, the software response will be selected.
                                     (for Non-HT response rate only)
    RESERVED30[30]               - (RO) Reserved bits
    BSSID03_SW_RESP_RATE_EN[31]  - (RW) Enables software response rate for BSSID03
                                     1'b0: Disable
                                     1'b1: Enable

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_EN_ADDR    BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_EN_MASK    0x80000000                // BSSID03_SW_RESP_RATE_EN[31]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_EN_SHFT    31
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_THRESHOLD_ADDR BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_THRESHOLD_MASK 0x30000000                // BSSID03_SW_RESP_RATE_THRESHOLD[29..28]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_THRESHOLD_SHFT 28
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_ADDR       BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_MASK       0x0E000000                // BSSID03_SW_RESP_RATE[27..25]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SW_RESP_RATE_SHFT       25
#define BN0_WF_TMAC_TOP_B3BRR0_Reserved_B3BRR0_0_ADDR          BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_Reserved_B3BRR0_0_MASK          0x01000000                // Reserved_B3BRR0_0[24]
#define BN0_WF_TMAC_TOP_B3BRR0_Reserved_B3BRR0_0_SHFT          24
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_MU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_MU_ACK_PE_MASK          0x000C0000                // BSSID03_MU_ACK_PE[19..18]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_MU_ACK_PE_SHFT          18
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SU_ACK_PE_ADDR          BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SU_ACK_PE_MASK          0x00030000                // BSSID03_SU_ACK_PE[17..16]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_SU_ACK_PE_SHFT          16
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_BW_OPT_ADDR         BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_BW_OPT_MASK         0x00008000                // BSSID03_ACK_BW_OPT[15]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_BW_OPT_SHFT         15
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_RATE_OPT_ADDR       BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_RATE_OPT_MASK       0x00007000                // BSSID03_ACK_RATE_OPT[14..12]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_ACK_RATE_OPT_SHFT       12
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_LG_RATE_MAP_ADDR        BN0_WF_TMAC_TOP_B3BRR0_ADDR
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_LG_RATE_MAP_MASK        0x00000FFF                // BSSID03_LG_RATE_MAP[11..0]
#define BN0_WF_TMAC_TOP_B3BRR0_BSSID03_LG_RATE_MAP_SHFT        0

/* =====================================================================================

  ---B3BRR1 (0x820E4000 + 0xDC)---

    BSSID03_RESP_ANT_ID[11..0]   - (RW) Global ANT_ID setting for BSSID03 response frame
                                     Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BSSID03_SPE_IDX[28..24]      - (RW) Spatial expansion table index for BSSID03
                                     (ACK/BA/CTS)
    RESERVED29[30..29]           - (RO) Reserved bits
    BSSID03_RESP_ANT_ID_SEL[31]  - (RW) Response ANT_ID mode for BSSID03
                                     1'b0: Select global response ANT_ID setting
                                     1'b1: Follow the peer's optimal TX ANT_ID (in WTBL)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_SEL_ADDR    BN0_WF_TMAC_TOP_B3BRR1_ADDR
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_SEL_MASK    0x80000000                // BSSID03_RESP_ANT_ID_SEL[31]
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_SEL_SHFT    31
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_SPE_IDX_ADDR            BN0_WF_TMAC_TOP_B3BRR1_ADDR
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_SPE_IDX_MASK            0x1F000000                // BSSID03_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_SPE_IDX_SHFT            24
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_ADDR        BN0_WF_TMAC_TOP_B3BRR1_ADDR
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_MASK        0x00000FFF                // BSSID03_RESP_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_B3BRR1_BSSID03_RESP_ANT_ID_SHFT        0

/* =====================================================================================

  ---QNCR0 (0x820E4000 + 0xE0)---

    QN0_SEQ_RANGE_IN_POWER2[3..0] - (RW) Specifies the sequence number range (in power of 2) for QoS_Null 0 frame
                                     The maximum value should be limited to 12, i.e. the valid values are from 0 to 12.
                                     For example, if this vaule is set to 4, HW will adopt sequence number for QoS-NULL within the range
                                     (QN_INITIAL_SEQ,  (QN_INITIAL_SEQ+2^4-1) ).
    QN0_INIT_SEQ[15..4]          - (RW) Initial sequence number for QoS_Null 0 frame
    QN1_SEQ_RANGE_IN_POWER2[19..16] - (RW) Specifies the sequence number range (in power of 2) for QoS_Null 1 frame
                                     The maximum value should be limited to 12, i.e. the valid values are from 0 to 12.
                                     For example, if this vaule is set to 4, HW will adopt sequence number for QoS-NULL within the range
                                     (QN_INITIAL_SEQ,  (QN_INITIAL_SEQ+2^4-1) ).
    QN1_INIT_SEQ[31..20]         - (RW) Initial sequence number for QoS_Null 1 frame

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_QNCR0_QN1_INIT_SEQ_ADDR                BN0_WF_TMAC_TOP_QNCR0_ADDR
#define BN0_WF_TMAC_TOP_QNCR0_QN1_INIT_SEQ_MASK                0xFFF00000                // QN1_INIT_SEQ[31..20]
#define BN0_WF_TMAC_TOP_QNCR0_QN1_INIT_SEQ_SHFT                20
#define BN0_WF_TMAC_TOP_QNCR0_QN1_SEQ_RANGE_IN_POWER2_ADDR     BN0_WF_TMAC_TOP_QNCR0_ADDR
#define BN0_WF_TMAC_TOP_QNCR0_QN1_SEQ_RANGE_IN_POWER2_MASK     0x000F0000                // QN1_SEQ_RANGE_IN_POWER2[19..16]
#define BN0_WF_TMAC_TOP_QNCR0_QN1_SEQ_RANGE_IN_POWER2_SHFT     16
#define BN0_WF_TMAC_TOP_QNCR0_QN0_INIT_SEQ_ADDR                BN0_WF_TMAC_TOP_QNCR0_ADDR
#define BN0_WF_TMAC_TOP_QNCR0_QN0_INIT_SEQ_MASK                0x0000FFF0                // QN0_INIT_SEQ[15..4]
#define BN0_WF_TMAC_TOP_QNCR0_QN0_INIT_SEQ_SHFT                4
#define BN0_WF_TMAC_TOP_QNCR0_QN0_SEQ_RANGE_IN_POWER2_ADDR     BN0_WF_TMAC_TOP_QNCR0_ADDR
#define BN0_WF_TMAC_TOP_QNCR0_QN0_SEQ_RANGE_IN_POWER2_MASK     0x0000000F                // QN0_SEQ_RANGE_IN_POWER2[3..0]
#define BN0_WF_TMAC_TOP_QNCR0_QN0_SEQ_RANGE_IN_POWER2_SHFT     0

/* =====================================================================================

  ---QNCR1 (0x820E4000 + 0xE4)---

    QN0_QOS_CTRL[15..0]          - (RW) Same definition as specified in standard for QoS_Null 0 frame
    QN1_QOS_CTRL[31..16]         - (RW) Same definition as specified in standard for QoS_Null 1 frame

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_QNCR1_QN1_QOS_CTRL_ADDR                BN0_WF_TMAC_TOP_QNCR1_ADDR
#define BN0_WF_TMAC_TOP_QNCR1_QN1_QOS_CTRL_MASK                0xFFFF0000                // QN1_QOS_CTRL[31..16]
#define BN0_WF_TMAC_TOP_QNCR1_QN1_QOS_CTRL_SHFT                16
#define BN0_WF_TMAC_TOP_QNCR1_QN0_QOS_CTRL_ADDR                BN0_WF_TMAC_TOP_QNCR1_ADDR
#define BN0_WF_TMAC_TOP_QNCR1_QN0_QOS_CTRL_MASK                0x0000FFFF                // QN0_QOS_CTRL[15..0]
#define BN0_WF_TMAC_TOP_QNCR1_QN0_QOS_CTRL_SHFT                0

/* =====================================================================================

  ---QNCR2 (0x820E4000 + 0xE8)---

    QN0_RESET_SEQ[0]             - (WO) Write 1 to reset the sequence number of QoS_Null0 frame to initial value.
                                     Writing 0 has no effect. Read always returns 0.
    QN1_RESET_SEQ[1]             - (WO) Write 1 to reset the sequence number of QoS_Null1 frame to initial value.
                                     Writing 0 has no effect. Read always returns 0.
    QN2_RESET_SEQ[2]             - (WO) Write 1 to reset the sequence number of QoS_Null2 frame to initial value.
                                     Writing 0 has no effect. Read always returns 0.
    QN3_RESET_SEQ[3]             - (WO) Write 1 to reset the sequence number of QoS_Null3 frame to initial value.
                                     Writing 0 has no effect. Read always returns 0.
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_QNCR2_QN3_RESET_SEQ_ADDR               BN0_WF_TMAC_TOP_QNCR2_ADDR
#define BN0_WF_TMAC_TOP_QNCR2_QN3_RESET_SEQ_MASK               0x00000008                // QN3_RESET_SEQ[3]
#define BN0_WF_TMAC_TOP_QNCR2_QN3_RESET_SEQ_SHFT               3
#define BN0_WF_TMAC_TOP_QNCR2_QN2_RESET_SEQ_ADDR               BN0_WF_TMAC_TOP_QNCR2_ADDR
#define BN0_WF_TMAC_TOP_QNCR2_QN2_RESET_SEQ_MASK               0x00000004                // QN2_RESET_SEQ[2]
#define BN0_WF_TMAC_TOP_QNCR2_QN2_RESET_SEQ_SHFT               2
#define BN0_WF_TMAC_TOP_QNCR2_QN1_RESET_SEQ_ADDR               BN0_WF_TMAC_TOP_QNCR2_ADDR
#define BN0_WF_TMAC_TOP_QNCR2_QN1_RESET_SEQ_MASK               0x00000002                // QN1_RESET_SEQ[1]
#define BN0_WF_TMAC_TOP_QNCR2_QN1_RESET_SEQ_SHFT               1
#define BN0_WF_TMAC_TOP_QNCR2_QN0_RESET_SEQ_ADDR               BN0_WF_TMAC_TOP_QNCR2_ADDR
#define BN0_WF_TMAC_TOP_QNCR2_QN0_RESET_SEQ_MASK               0x00000001                // QN0_RESET_SEQ[0]
#define BN0_WF_TMAC_TOP_QNCR2_QN0_RESET_SEQ_SHFT               0

/* =====================================================================================

  ---QNCR3 (0x820E4000 + 0xEC)---

    QN2_SEQ_RANGE_IN_POWER2[3..0] - (RW) Specifies the sequence number range (in power of 2) for QoS_Null 2 frame
                                     The maximum value should be limited to 12, i.e. the valid values are from 0 to 12.
                                     For example, if this vaule is set to 4, HW will adopt sequence number for QoS-NULL within the range
                                     (QN_INITIAL_SEQ,  (QN_INITIAL_SEQ+2^4-1) ).
    QN2_INIT_SEQ[15..4]          - (RW) Initial sequence number for QoS_Null 2 frame
    QN3_SEQ_RANGE_IN_POWER2[19..16] - (RW) Specifies the sequence number range (in power of 2) for QoS_Null 3 frame
                                     The maximum value should be limited to 12, i.e. the valid values are from 0 to 12.
                                     For example, if this vaule is set to 4, HW will adopt sequence number for QoS-NULL within the range
                                     (QN_INITIAL_SEQ,  (QN_INITIAL_SEQ+2^4-1) ).
    QN3_INIT_SEQ[31..20]         - (RW) Initial sequence number for QoS_Null 3 frame

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_QNCR3_QN3_INIT_SEQ_ADDR                BN0_WF_TMAC_TOP_QNCR3_ADDR
#define BN0_WF_TMAC_TOP_QNCR3_QN3_INIT_SEQ_MASK                0xFFF00000                // QN3_INIT_SEQ[31..20]
#define BN0_WF_TMAC_TOP_QNCR3_QN3_INIT_SEQ_SHFT                20
#define BN0_WF_TMAC_TOP_QNCR3_QN3_SEQ_RANGE_IN_POWER2_ADDR     BN0_WF_TMAC_TOP_QNCR3_ADDR
#define BN0_WF_TMAC_TOP_QNCR3_QN3_SEQ_RANGE_IN_POWER2_MASK     0x000F0000                // QN3_SEQ_RANGE_IN_POWER2[19..16]
#define BN0_WF_TMAC_TOP_QNCR3_QN3_SEQ_RANGE_IN_POWER2_SHFT     16
#define BN0_WF_TMAC_TOP_QNCR3_QN2_INIT_SEQ_ADDR                BN0_WF_TMAC_TOP_QNCR3_ADDR
#define BN0_WF_TMAC_TOP_QNCR3_QN2_INIT_SEQ_MASK                0x0000FFF0                // QN2_INIT_SEQ[15..4]
#define BN0_WF_TMAC_TOP_QNCR3_QN2_INIT_SEQ_SHFT                4
#define BN0_WF_TMAC_TOP_QNCR3_QN2_SEQ_RANGE_IN_POWER2_ADDR     BN0_WF_TMAC_TOP_QNCR3_ADDR
#define BN0_WF_TMAC_TOP_QNCR3_QN2_SEQ_RANGE_IN_POWER2_MASK     0x0000000F                // QN2_SEQ_RANGE_IN_POWER2[3..0]
#define BN0_WF_TMAC_TOP_QNCR3_QN2_SEQ_RANGE_IN_POWER2_SHFT     0

/* =====================================================================================

  ---QNCR4 (0x820E4000 + 0xF0)---

    QN2_QOS_CTRL[15..0]          - (RW) Same definition as specified in standard for QoS_Null 2 frame
    QN3_QOS_CTRL[31..16]         - (RW) Same definition as specified in standard for QoS_Null 3 frame

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_QNCR4_QN3_QOS_CTRL_ADDR                BN0_WF_TMAC_TOP_QNCR4_ADDR
#define BN0_WF_TMAC_TOP_QNCR4_QN3_QOS_CTRL_MASK                0xFFFF0000                // QN3_QOS_CTRL[31..16]
#define BN0_WF_TMAC_TOP_QNCR4_QN3_QOS_CTRL_SHFT                16
#define BN0_WF_TMAC_TOP_QNCR4_QN2_QOS_CTRL_ADDR                BN0_WF_TMAC_TOP_QNCR4_ADDR
#define BN0_WF_TMAC_TOP_QNCR4_QN2_QOS_CTRL_MASK                0x0000FFFF                // QN2_QOS_CTRL[15..0]
#define BN0_WF_TMAC_TOP_QNCR4_QN2_QOS_CTRL_SHFT                0

/* =====================================================================================

  ---CTCR0 (0x820E4000 + 0xF4)---

    INS_DDLMT_REFTIME[5..0]      - (RW) Dummy delimiter insertion reference time
                                     Unit: us
                                     Separate reference time to 5 ranges to count dummy delimiter insertion result
                                     Range 0: count = 0
                                     Range 1: 0 <  count <  1/4 ref. time
                                     Range 2: 1/4 <= count <  1/2 ref. time
                                     Range 3: 1/2 <= count <  3/4 ref. time
                                     Range 4: 3/4 <= count <= 1 ref. time
    Reserved_CTCR0_1[16..6]      - (RW) Reserved
    INS_DDLMT_EN[17]             - (RW) Dummy delimiter insertion control
                                     0: Disable
                                     1: Enable
    INS_DDLMT_VHT_SMPDU_EN[18]   - (RW) VHT single MPDU dummy delimiter insertion control
                                     1'b0: Disable
                                     1'b1: Enable
    Reserved_CTCR0_0[31..19]     - (RW) Reserved

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_0_ADDR            BN0_WF_TMAC_TOP_CTCR0_ADDR
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_0_MASK            0xFFF80000                // Reserved_CTCR0_0[31..19]
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_0_SHFT            19
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_VHT_SMPDU_EN_ADDR      BN0_WF_TMAC_TOP_CTCR0_ADDR
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_VHT_SMPDU_EN_MASK      0x00040000                // INS_DDLMT_VHT_SMPDU_EN[18]
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_VHT_SMPDU_EN_SHFT      18
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_EN_ADDR                BN0_WF_TMAC_TOP_CTCR0_ADDR
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_EN_MASK                0x00020000                // INS_DDLMT_EN[17]
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_EN_SHFT                17
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_1_ADDR            BN0_WF_TMAC_TOP_CTCR0_ADDR
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_1_MASK            0x0001FFC0                // Reserved_CTCR0_1[16..6]
#define BN0_WF_TMAC_TOP_CTCR0_Reserved_CTCR0_1_SHFT            6
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_REFTIME_ADDR           BN0_WF_TMAC_TOP_CTCR0_ADDR
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_REFTIME_MASK           0x0000003F                // INS_DDLMT_REFTIME[5..0]
#define BN0_WF_TMAC_TOP_CTCR0_INS_DDLMT_REFTIME_SHFT           0

/* =====================================================================================

  ---CTCR1 (0x820E4000 + 0xF8)---

    INS_DDLMT_DENSITY[5..0]      - (RW) dummy delimiter insertion density
                                     6'h0: 1 dummy delimiter/per 1T mac_1x_ck
                                     6'h1: 1 dummy delimiter/per 2T mac_1x_ck
                                     an so on
    Reserved_CTCR1_0[15..6]      - (RW) Reserved
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_CTCR1_Reserved_CTCR1_0_ADDR            BN0_WF_TMAC_TOP_CTCR1_ADDR
#define BN0_WF_TMAC_TOP_CTCR1_Reserved_CTCR1_0_MASK            0x0000FFC0                // Reserved_CTCR1_0[15..6]
#define BN0_WF_TMAC_TOP_CTCR1_Reserved_CTCR1_0_SHFT            6
#define BN0_WF_TMAC_TOP_CTCR1_INS_DDLMT_DENSITY_ADDR           BN0_WF_TMAC_TOP_CTCR1_ADDR
#define BN0_WF_TMAC_TOP_CTCR1_INS_DDLMT_DENSITY_MASK           0x0000003F                // INS_DDLMT_DENSITY[5..0]
#define BN0_WF_TMAC_TOP_CTCR1_INS_DDLMT_DENSITY_SHFT           0

/* =====================================================================================

  ---OMDTR (0x820E4000 + 0xFC)---

    OFDMA_MU_MDRDY_TOUT[15..0]   - (RW) OFDMA-MU MDRDY response timeout time
                                     Same as CCK_MDRDY_Timeout.
                                     Note: This value is available when the expected RX rate is OFDMA-MU (TX HE_TB)  / HE_TB (TX Trigger) rate.
    OFDMA_MU_CCA_TOUT[31..16]    - (RW) OFDMA-MU CCA response timeout time
                                     Same as CCK_CCA_Timeout.
                                     Note: This value is available when the expected RX rate is OFDMA-MU (TX HE_TB) / HE_TB (TX Trigger) rate.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_CCA_TOUT_ADDR           BN0_WF_TMAC_TOP_OMDTR_ADDR
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_CCA_TOUT_MASK           0xFFFF0000                // OFDMA_MU_CCA_TOUT[31..16]
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_CCA_TOUT_SHFT           16
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_MDRDY_TOUT_ADDR         BN0_WF_TMAC_TOP_OMDTR_ADDR
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_MDRDY_TOUT_MASK         0x0000FFFF                // OFDMA_MU_MDRDY_TOUT[15..0]
#define BN0_WF_TMAC_TOP_OMDTR_OFDMA_MU_MDRDY_TOUT_SHFT         0

/* =====================================================================================

  ---B0BRR4 (0x820E4000 + 0x108)---

    BSSID00_HE_ER_SU_RATE_MAP[2..0] - (RW) HE_ER_SU MCS bitmap for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[2:0]: HE_ER_SU MCS2~MCS0
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID00_HE_SU_RATE_MAP[15..4] - (RW) HE_SU MCS bitmap for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[11:0]: HE_SU MCS11~MCS0
    BSSID00_RESP_HELTF_TYPE[17..16] - (RW) HE_LTF_TYPE for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA)
                                     2'h0: 1X HE_LTF
                                     2'h1: 2X HE_LTF
                                     2'h2: 4X HE_LTF 
                                     2'h3: Reserved
    BSSID00_RESP_GI_TYPE[19..18] - (RW) HE_GI_TYPE for BSSID00/BSSID1x/BSSID2x (ACK/BA/MSBA)
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI 
                                     2'h3: Reserved
    BSSID00_RESP_MU2SU_RATE[26..20] - (RW) MU2SU Response rate  for BSSID00/BSSID1x/BSSID2x (MSBA)
                                     In some case, HW need to replace TXCMD assigned OFDMA_BA by SU MSBA, the response rate will assigned by this CR
                                     Bit[6]: TX MOD
                                     1'h0: Non-HT OFDM
                                     1'h1: HE_ER_SU
                                     Bit[5:0]: rate / MCS
                                     for Non-HT OFDM
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     for HE_ER_SU
                                     Bit[5]: HE_ER_SU 106Tone
                                     1'h0: use 242 tone
                                     1'h1: use 1-6 tone
                                     Bit[4]: DCM
                                     1'h0: No DCM
                                     1'h1: DCM rate
                                     Bit[3:0]: MCS
                                     4'h0: MCS0
                                     4'h1: MCS1
                                     4'h2: MCS2
                                     others: reserved
    BSSID00_RESP_SU_DCM[27]      - (RW) HE_SU MCS0 DCM for BSSID00/BSSID1x/BSSID2x 
                                     1'b0: disable DCM support for HE_SU MCS
                                     1'b1: if the response rate is HE_SU MCS0, follow the RX rate DCM
    BSSID00_RESP_DOPPLER[28]     - (RW) Doppler for BSSID00/BSSID1x/BSSID2x 
                                     1'b0: Not support
                                     1'b1: Support
    BSSID00_RESP_LDPC[29]        - (RW) Force LDPC for BSSID00/BSSID1x/BSSID2x
                                     (ACK/BA/CTS)
                                     1'b0: if the response rate supports BCC, use BSS, otherwise use LDPC
                                     1'b1: always use LDPC
    BSSID00_RESP_TXMOD_MODE[30]  - (RW) TXMOD for BSSID00/BSSID1x/BSSID2x 
                                     1'b0: follow standard defined rule
                                     1'b1: use HE_ER_SU if response to HE_ER_SU, otherwise use non-HT MOD
    BSSID00_RESP_STBC_MODE[31]   - (RW) STBC mode for BSSID00/BSSID1x/BSSID2x
                                     1'b0: No STBC
                                     1'b1: USE STBC when response to HE_ER_SU / HE_SU with STBC, otherwise disable STBC

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_STBC_MODE_ADDR     BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_STBC_MODE_MASK     0x80000000                // BSSID00_RESP_STBC_MODE[31]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_STBC_MODE_SHFT     31
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_TXMOD_MODE_ADDR    BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_TXMOD_MODE_MASK    0x40000000                // BSSID00_RESP_TXMOD_MODE[30]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_TXMOD_MODE_SHFT    30
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_LDPC_ADDR          BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_LDPC_MASK          0x20000000                // BSSID00_RESP_LDPC[29]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_LDPC_SHFT          29
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_DOPPLER_ADDR       BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_DOPPLER_MASK       0x10000000                // BSSID00_RESP_DOPPLER[28]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_DOPPLER_SHFT       28
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_SU_DCM_ADDR        BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_SU_DCM_MASK        0x08000000                // BSSID00_RESP_SU_DCM[27]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_SU_DCM_SHFT        27
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_MU2SU_RATE_ADDR    BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_MU2SU_RATE_MASK    0x07F00000                // BSSID00_RESP_MU2SU_RATE[26..20]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_MU2SU_RATE_SHFT    20
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_GI_TYPE_ADDR       BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_GI_TYPE_MASK       0x000C0000                // BSSID00_RESP_GI_TYPE[19..18]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_GI_TYPE_SHFT       18
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_HELTF_TYPE_ADDR    BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_HELTF_TYPE_MASK    0x00030000                // BSSID00_RESP_HELTF_TYPE[17..16]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_RESP_HELTF_TYPE_SHFT    16
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_SU_RATE_MAP_ADDR     BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_SU_RATE_MAP_MASK     0x0000FFF0                // BSSID00_HE_SU_RATE_MAP[15..4]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_SU_RATE_MAP_SHFT     4
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_ER_SU_RATE_MAP_ADDR  BN0_WF_TMAC_TOP_B0BRR4_ADDR
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_ER_SU_RATE_MAP_MASK  0x00000007                // BSSID00_HE_ER_SU_RATE_MAP[2..0]
#define BN0_WF_TMAC_TOP_B0BRR4_BSSID00_HE_ER_SU_RATE_MAP_SHFT  0

/* =====================================================================================

  ---B1BRR2 (0x820E4000 + 0x110)---

    BSSID01_HE_ER_SU_RATE_MAP[2..0] - (RW) HE_ER_SU MCS bitmap for BSSID01 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[2:0]: HE_ER_SU MCS2~MCS0
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID01_HE_SU_RATE_MAP[15..4] - (RW) HE_SU MCS bitmap for BSSID01 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[11:0]: HE_SU MCS11~MCS0
    BSSID01_RESP_HELTF_TYPE[17..16] - (RW) HE_LTF_TYPE for BSSID01 (ACK/BA/MSBA)
                                     2'h0: 1X HE_LTF
                                     2'h1: 2X HE_LTF
                                     2'h2: 4X HE_LTF 
                                     2'h3: Reserved
    BSSID01_RESP_GI_TYPE[19..18] - (RW) HE_GI_TYPE for BSSID01 (ACK/BA/MSBA)
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI 
                                     2'h3: Reserved
    BSSID01_RESP_MU2SU_RATE[26..20] - (RW) MU2SU Response rate  for BSSID01
                                     (MSBA)
                                     In some case, HW need to replace TXCMD assigned OFDMA_BA by SU MSBA, the response rate will assigned by this CR
                                     Bit[6]: TX MOD
                                     1'h0: Non-HT OFDM
                                     1'h1: HE_ER_SU
                                     Bit[5:0]: rate / MCS
                                     for Non-HT OFDM
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     for HE_ER_SU
                                     Bit[5]: HE_ER_SU 106Tone
                                     1'h0: use 242 tone
                                     1'h1: use 1-6 tone
                                     Bit[4]: DCM
                                     1'h0: No DCM
                                     1'h1: DCM rate
                                     Bit[3:0]: MCS
                                     4'h0: MCS0
                                     4'h1: MCS1
                                     4'h2: MCS2
                                     others: reserved
    BSSID01_RESP_SU_DCM[27]      - (RW) HE_SU MCS0 DCM for BSSID01 
                                     1'b0: disable DCM support for HE_SU MCS
                                     1'b1: if the response rate is HE_SU MCS0, follow the RX rate DCM
    BSSID01_RESP_DOPPLER[28]     - (RW) Doppler for BSSID01 
                                     1'b0: Not support
                                     1'b1: Support
    BSSID01_RESP_LDPC[29]        - (RW) Force LDPC for BSSID01
                                     (ACK/BA/CTS)
                                     1'b0: if the response rate supports BCC, use BSS, otherwise use LDPC
                                     1'b1: always use LDPC
    BSSID01_RESP_TXMOD_MODE[30]  - (RW) TXMOD for BSSID01 
                                     1'b0: follow standard defined rule
                                     1'b1: use HE_ER_SU if response to HE_ER_SU, otherwise use non-HT MOD
    BSSID01_RESP_STBC_MODE[31]   - (RW) STBC mode for BSSID01
                                     1'b0: No STBC
                                     1'b1: USE STBC when response to HE_ER_SU / HE_SU with STBC, otherwise disable STBC

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_STBC_MODE_ADDR     BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_STBC_MODE_MASK     0x80000000                // BSSID01_RESP_STBC_MODE[31]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_STBC_MODE_SHFT     31
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_TXMOD_MODE_ADDR    BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_TXMOD_MODE_MASK    0x40000000                // BSSID01_RESP_TXMOD_MODE[30]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_TXMOD_MODE_SHFT    30
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_LDPC_ADDR          BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_LDPC_MASK          0x20000000                // BSSID01_RESP_LDPC[29]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_LDPC_SHFT          29
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_DOPPLER_ADDR       BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_DOPPLER_MASK       0x10000000                // BSSID01_RESP_DOPPLER[28]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_DOPPLER_SHFT       28
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_SU_DCM_ADDR        BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_SU_DCM_MASK        0x08000000                // BSSID01_RESP_SU_DCM[27]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_SU_DCM_SHFT        27
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_MU2SU_RATE_ADDR    BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_MU2SU_RATE_MASK    0x07F00000                // BSSID01_RESP_MU2SU_RATE[26..20]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_MU2SU_RATE_SHFT    20
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_GI_TYPE_ADDR       BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_GI_TYPE_MASK       0x000C0000                // BSSID01_RESP_GI_TYPE[19..18]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_GI_TYPE_SHFT       18
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_HELTF_TYPE_ADDR    BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_HELTF_TYPE_MASK    0x00030000                // BSSID01_RESP_HELTF_TYPE[17..16]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_RESP_HELTF_TYPE_SHFT    16
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_SU_RATE_MAP_ADDR     BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_SU_RATE_MAP_MASK     0x0000FFF0                // BSSID01_HE_SU_RATE_MAP[15..4]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_SU_RATE_MAP_SHFT     4
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_ER_SU_RATE_MAP_ADDR  BN0_WF_TMAC_TOP_B1BRR2_ADDR
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_ER_SU_RATE_MAP_MASK  0x00000007                // BSSID01_HE_ER_SU_RATE_MAP[2..0]
#define BN0_WF_TMAC_TOP_B1BRR2_BSSID01_HE_ER_SU_RATE_MAP_SHFT  0

/* =====================================================================================

  ---B2BRR2 (0x820E4000 + 0x114)---

    BSSID02_HE_ER_SU_RATE_MAP[2..0] - (RW) HE_ER_SU MCS bitmap for BSSID02 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[2:0]: HE_ER_SU MCS2~MCS0
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID02_HE_SU_RATE_MAP[15..4] - (RW) HE_SU MCS bitmap for BSSID02 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[11:0]: HE_SU MCS11~MCS0
    BSSID02_RESP_HELTF_TYPE[17..16] - (RW) HE_LTF_TYPE for BSSID02 (ACK/BA/MSBA)
                                     2'h0: 1X HE_LTF
                                     2'h1: 2X HE_LTF
                                     2'h2: 4X HE_LTF 
                                     2'h3: Reserved
    RESERVED18[19..18]           - (RO) Reserved bits
    BSSID02_RESP_MU2SU_RATE[26..20] - (RW) MU2SU Response rate  for BSSID02
                                     (MSBA)
                                     In some case, HW need to replace TXCMD assigned OFDMA_BA by SU MSBA, the response rate will assigned by this CR
                                     Bit[6]: TX MOD
                                     1'h0: Non-HT OFDM
                                     1'h1: HE_ER_SU
                                     Bit[5:0]: rate / MCS
                                     for Non-HT OFDM
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     for HE_ER_SU
                                     Bit[5]: HE_ER_SU 106Tone
                                     1'h0: use 242 tone
                                     1'h1: use 1-6 tone
                                     Bit[4]: DCM
                                     1'h0: No DCM
                                     1'h1: DCM rate
                                     Bit[3:0]: MCS
                                     4'h0: MCS0
                                     4'h1: MCS1
                                     4'h2: MCS2
                                     others: reserved
    BSSID02_RESP_SU_DCM[27]      - (RW) HE_SU MCS0 DCM for BSSID02
                                     1'b0: disable DCM support for HE_SU MCS
                                     1'b1: if the response rate is HE_SU MCS0, follow the RX rate DCM
    BSSID02_RESP_DOPPLER[28]     - (RW) Doppler for BSSID02 
                                     1'b0: Not support
                                     1'b1: Support
    BSSID02_RESP_LDPC[29]        - (RW) Force LDPC for BSSID02
                                     (ACK/BA/CTS)
                                     1'b0: if the response rate supports BCC, use BSS, otherwise use LDPC
                                     1'b1: always use LDPC
    BSSID02_RESP_TXMOD_MODE[30]  - (RW) TXMOD for BSSID02 
                                     1'b0: follow standard defined rule
                                     1'b1: use HE_ER_SU if response to HE_ER_SU, otherwise use non-HT MOD
    BSSID02_RESP_STBC_MODE[31]   - (RW) STBC mode for BSSID02
                                     1'b0: No STBC
                                     1'b1: USE STBC when response to HE_ER_SU / HE_SU with STBC, otherwise disable STBC

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_STBC_MODE_ADDR     BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_STBC_MODE_MASK     0x80000000                // BSSID02_RESP_STBC_MODE[31]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_STBC_MODE_SHFT     31
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_TXMOD_MODE_ADDR    BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_TXMOD_MODE_MASK    0x40000000                // BSSID02_RESP_TXMOD_MODE[30]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_TXMOD_MODE_SHFT    30
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_LDPC_ADDR          BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_LDPC_MASK          0x20000000                // BSSID02_RESP_LDPC[29]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_LDPC_SHFT          29
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_DOPPLER_ADDR       BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_DOPPLER_MASK       0x10000000                // BSSID02_RESP_DOPPLER[28]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_DOPPLER_SHFT       28
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_SU_DCM_ADDR        BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_SU_DCM_MASK        0x08000000                // BSSID02_RESP_SU_DCM[27]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_SU_DCM_SHFT        27
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_MU2SU_RATE_ADDR    BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_MU2SU_RATE_MASK    0x07F00000                // BSSID02_RESP_MU2SU_RATE[26..20]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_MU2SU_RATE_SHFT    20
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_HELTF_TYPE_ADDR    BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_HELTF_TYPE_MASK    0x00030000                // BSSID02_RESP_HELTF_TYPE[17..16]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_RESP_HELTF_TYPE_SHFT    16
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_SU_RATE_MAP_ADDR     BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_SU_RATE_MAP_MASK     0x0000FFF0                // BSSID02_HE_SU_RATE_MAP[15..4]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_SU_RATE_MAP_SHFT     4
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_ER_SU_RATE_MAP_ADDR  BN0_WF_TMAC_TOP_B2BRR2_ADDR
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_ER_SU_RATE_MAP_MASK  0x00000007                // BSSID02_HE_ER_SU_RATE_MAP[2..0]
#define BN0_WF_TMAC_TOP_B2BRR2_BSSID02_HE_ER_SU_RATE_MAP_SHFT  0

/* =====================================================================================

  ---B3BRR2 (0x820E4000 + 0x118)---

    BSSID03_HE_ER_SU_RATE_MAP[2..0] - (RW) HE_ER_SU MCS bitmap for BSSID03 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[2:0]: HE_ER_SU MCS2~MCS0
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID03_HE_SU_RATE_MAP[15..4] - (RW) HE_SU MCS bitmap for BSSID03 (ACK/BA/MSBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[11:0]: HE_SU MCS11~MCS0
    BSSID03_RESP_HELTF_TYPE[17..16] - (RW) HE_LTF_TYPE for BSSID03 (ACK/BA/MSBA)
                                     2'h0: 1X HE_LTF
                                     2'h1: 2X HE_LTF
                                     2'h2: 4X HE_LTF 
                                     2'h3: Reserved
    BSSID03_RESP_GI_TYPE[19..18] - (RW) HE_GI_TYPE for BSSID03 (ACK/BA/MSBA)
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI 
                                     2'h3: Reserved
    BSSID03_RESP_MU2SU_RATE[26..20] - (RW) MU2SU Response rate  for BSSID03
                                     (MSBA)
                                     In some case, HW need to replace TXCMD assigned OFDMA_BA by SU MSBA, the response rate will assigned by this CR
                                     Bit[6]: TX MOD
                                     1'h0: Non-HT OFDM
                                     1'h1: HE_ER_SU
                                     Bit[5:0]: rate / MCS
                                     for Non-HT OFDM
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     for HE_ER_SU
                                     Bit[5]: HE_ER_SU 106Tone
                                     1'h0: use 242 tone
                                     1'h1: use 1-6 tone
                                     Bit[4]: DCM
                                     1'h0: No DCM
                                     1'h1: DCM rate
                                     Bit[3:0]: MCS
                                     4'h0: MCS0
                                     4'h1: MCS1
                                     4'h2: MCS2
                                     others: reserved
    BSSID03_RESP_SU_DCM[27]      - (RW) HE_SU MCS0 DCM for BSSID03
                                     1'b0: disable DCM support for HE_SU MCS
                                     1'b1: if the response rate is HE_SU MCS0, follow the RX rate DCM
    BSSID03_RESP_DOPPLER[28]     - (RW) Doppler for BSSID03 
                                     1'b0: Not support
                                     1'b1: Support
    BSSID03_RESP_LDPC[29]        - (RW) Force LDPC for BSSID03
                                     (ACK/BA/CTS)
                                     1'b0: if the response rate supports BCC, use BSS, otherwise use LDPC
                                     1'b1: always use LDPC
    BSSID03_RESP_TXMOD_MODE[30]  - (RW) TXMOD for BSSID03 
                                     1'b0: follow standard defined rule
                                     1'b1: use HE_ER_SU if response to HE_ER_SU, otherwise use non-HT MOD
    BSSID03_RESP_STBC_MODE[31]   - (RW) STBC mode for BSSID03
                                     1'b0: No STBC
                                     1'b1: USE STBC when response to HE_ER_SU / HE_SU with STBC, otherwise disable STBC

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_STBC_MODE_ADDR     BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_STBC_MODE_MASK     0x80000000                // BSSID03_RESP_STBC_MODE[31]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_STBC_MODE_SHFT     31
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_TXMOD_MODE_ADDR    BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_TXMOD_MODE_MASK    0x40000000                // BSSID03_RESP_TXMOD_MODE[30]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_TXMOD_MODE_SHFT    30
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_LDPC_ADDR          BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_LDPC_MASK          0x20000000                // BSSID03_RESP_LDPC[29]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_LDPC_SHFT          29
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_DOPPLER_ADDR       BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_DOPPLER_MASK       0x10000000                // BSSID03_RESP_DOPPLER[28]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_DOPPLER_SHFT       28
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_SU_DCM_ADDR        BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_SU_DCM_MASK        0x08000000                // BSSID03_RESP_SU_DCM[27]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_SU_DCM_SHFT        27
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_MU2SU_RATE_ADDR    BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_MU2SU_RATE_MASK    0x07F00000                // BSSID03_RESP_MU2SU_RATE[26..20]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_MU2SU_RATE_SHFT    20
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_GI_TYPE_ADDR       BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_GI_TYPE_MASK       0x000C0000                // BSSID03_RESP_GI_TYPE[19..18]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_GI_TYPE_SHFT       18
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_HELTF_TYPE_ADDR    BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_HELTF_TYPE_MASK    0x00030000                // BSSID03_RESP_HELTF_TYPE[17..16]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_RESP_HELTF_TYPE_SHFT    16
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_SU_RATE_MAP_ADDR     BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_SU_RATE_MAP_MASK     0x0000FFF0                // BSSID03_HE_SU_RATE_MAP[15..4]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_SU_RATE_MAP_SHFT     4
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_ER_SU_RATE_MAP_ADDR  BN0_WF_TMAC_TOP_B3BRR2_ADDR
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_ER_SU_RATE_MAP_MASK  0x00000007                // BSSID03_HE_ER_SU_RATE_MAP[2..0]
#define BN0_WF_TMAC_TOP_B3BRR2_BSSID03_HE_ER_SU_RATE_MAP_SHFT  0

/* =====================================================================================

  ---SPCR (0x820E4000 + 0x11C)---

    HW_DFL1_OPT0[0]              - (RW) Aborts current TX sequence when received RDG packet cannot match WTBL entry
                                     1'b0: Disable
                                     1'b1: Enable
    HW_DFL1_OPT1[1]              - (RW) Continuous TX response packet when RDG packet is received without airend
                                     1'b0: Disable
                                     1'b1: Enable
    B0_OFDM_T2R_RX_OFF[2]        - (RW) Enable OFDM T2R 6uS (signal extension) Rx OFF time, 0: 6uS Rx ON, 1: 6uS Rx OFF
    SPCR_H_RSV1[3]               - (RW) Reserved
    APS_CCA_OFF_TIME[7..4]       - (RW) CCA detect off time when RX on during GREEN AP period, Unit: 1uS
    SPCR_H_RSV2[15..8]           - (RW) Reserved
    B0_ETXBF_EXTRA_ABT_EN[16]    - (RW) Enable etxbf extra abort beamform report frame and Tx/Rx happen in the same time
    SPCR_L_RSV1[19..17]          - (RW) Reserved
    APS_CCA_DET_OFF[20]          - (RW) Enable CCA detect off when RX on during GREEN AP period
    COEX_TXPWR_CTL_EN[21]        - (RW) COEX Max. TX Power control
                                     0: disable TX Power control
                                     1: enable TX power control
    SPCR_L_RSV2[22]              - (RW) Spare control register and default value are all 0.
    SGI_ECO_DIS[23]              - (RW) SGI ECO control
                                     0: disable SGI ECO
                                     1: enable SGI ECO
    SPCR_L_RSV0[31..24]          - (RW) Spare control register and default value are all 0.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV0_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV0_MASK                  0xFF000000                // SPCR_L_RSV0[31..24]
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV0_SHFT                  24
#define BN0_WF_TMAC_TOP_SPCR_SGI_ECO_DIS_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SGI_ECO_DIS_MASK                  0x00800000                // SGI_ECO_DIS[23]
#define BN0_WF_TMAC_TOP_SPCR_SGI_ECO_DIS_SHFT                  23
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV2_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV2_MASK                  0x00400000                // SPCR_L_RSV2[22]
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV2_SHFT                  22
#define BN0_WF_TMAC_TOP_SPCR_COEX_TXPWR_CTL_EN_ADDR            BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_COEX_TXPWR_CTL_EN_MASK            0x00200000                // COEX_TXPWR_CTL_EN[21]
#define BN0_WF_TMAC_TOP_SPCR_COEX_TXPWR_CTL_EN_SHFT            21
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_DET_OFF_ADDR              BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_DET_OFF_MASK              0x00100000                // APS_CCA_DET_OFF[20]
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_DET_OFF_SHFT              20
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV1_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV1_MASK                  0x000E0000                // SPCR_L_RSV1[19..17]
#define BN0_WF_TMAC_TOP_SPCR_SPCR_L_RSV1_SHFT                  17
#define BN0_WF_TMAC_TOP_SPCR_B0_ETXBF_EXTRA_ABT_EN_ADDR        BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_B0_ETXBF_EXTRA_ABT_EN_MASK        0x00010000                // B0_ETXBF_EXTRA_ABT_EN[16]
#define BN0_WF_TMAC_TOP_SPCR_B0_ETXBF_EXTRA_ABT_EN_SHFT        16
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV2_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV2_MASK                  0x0000FF00                // SPCR_H_RSV2[15..8]
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV2_SHFT                  8
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_OFF_TIME_ADDR             BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_OFF_TIME_MASK             0x000000F0                // APS_CCA_OFF_TIME[7..4]
#define BN0_WF_TMAC_TOP_SPCR_APS_CCA_OFF_TIME_SHFT             4
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV1_ADDR                  BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV1_MASK                  0x00000008                // SPCR_H_RSV1[3]
#define BN0_WF_TMAC_TOP_SPCR_SPCR_H_RSV1_SHFT                  3
#define BN0_WF_TMAC_TOP_SPCR_B0_OFDM_T2R_RX_OFF_ADDR           BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_B0_OFDM_T2R_RX_OFF_MASK           0x00000004                // B0_OFDM_T2R_RX_OFF[2]
#define BN0_WF_TMAC_TOP_SPCR_B0_OFDM_T2R_RX_OFF_SHFT           2
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT1_ADDR                 BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT1_MASK                 0x00000002                // HW_DFL1_OPT1[1]
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT1_SHFT                 1
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT0_ADDR                 BN0_WF_TMAC_TOP_SPCR_ADDR
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT0_MASK                 0x00000001                // HW_DFL1_OPT0[0]
#define BN0_WF_TMAC_TOP_SPCR_HW_DFL1_OPT0_SHFT                 0

/* =====================================================================================

  ---DBGR0 (0x820E4000 + 0x120)---

    DBGR0[31..0]                 - (RO) Debug register

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR0_DBGR0_ADDR                       BN0_WF_TMAC_TOP_DBGR0_ADDR
#define BN0_WF_TMAC_TOP_DBGR0_DBGR0_MASK                       0xFFFFFFFF                // DBGR0[31..0]
#define BN0_WF_TMAC_TOP_DBGR0_DBGR0_SHFT                       0

/* =====================================================================================

  ---DBGR1 (0x820E4000 + 0x124)---

    DBGR1[31..0]                 - (RO) Debug register

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR1_DBGR1_ADDR                       BN0_WF_TMAC_TOP_DBGR1_ADDR
#define BN0_WF_TMAC_TOP_DBGR1_DBGR1_MASK                       0xFFFFFFFF                // DBGR1[31..0]
#define BN0_WF_TMAC_TOP_DBGR1_DBGR1_SHFT                       0

/* =====================================================================================

  ---DBGR2 (0x820E4000 + 0x128)---

    DBGR2[31..0]                 - (RO) Debug register

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR2_DBGR2_ADDR                       BN0_WF_TMAC_TOP_DBGR2_ADDR
#define BN0_WF_TMAC_TOP_DBGR2_DBGR2_MASK                       0xFFFFFFFF                // DBGR2[31..0]
#define BN0_WF_TMAC_TOP_DBGR2_DBGR2_SHFT                       0

/* =====================================================================================

  ---DBGR3 (0x820E4000 + 0x12C)---

    DBGR3[31..0]                 - (RO) Debug register
                                     bit[31:16]: internal event counter
                                     bit[15:0]: COEX "force UPH to 0" event counter

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR3_DBGR3_ADDR                       BN0_WF_TMAC_TOP_DBGR3_ADDR
#define BN0_WF_TMAC_TOP_DBGR3_DBGR3_MASK                       0xFFFFFFFF                // DBGR3[31..0]
#define BN0_WF_TMAC_TOP_DBGR3_DBGR3_SHFT                       0

/* =====================================================================================

  ---DBGR4 (0x820E4000 + 0x130)---

    DBGR4[31..0]                 - (RO) Debug register (BN0 TXV1)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR4_DBGR4_ADDR                       BN0_WF_TMAC_TOP_DBGR4_ADDR
#define BN0_WF_TMAC_TOP_DBGR4_DBGR4_MASK                       0xFFFFFFFF                // DBGR4[31..0]
#define BN0_WF_TMAC_TOP_DBGR4_DBGR4_SHFT                       0

/* =====================================================================================

  ---DBGR5 (0x820E4000 + 0x134)---

    DBGR5[31..0]                 - (RO) Debug register (BN0 TXV2)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR5_DBGR5_ADDR                       BN0_WF_TMAC_TOP_DBGR5_ADDR
#define BN0_WF_TMAC_TOP_DBGR5_DBGR5_MASK                       0xFFFFFFFF                // DBGR5[31..0]
#define BN0_WF_TMAC_TOP_DBGR5_DBGR5_SHFT                       0

/* =====================================================================================

  ---DBGR6 (0x820E4000 + 0x138)---

    DBGR6[31..0]                 - (RO) Debug register (BN0 TXV3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR6_DBGR6_ADDR                       BN0_WF_TMAC_TOP_DBGR6_ADDR
#define BN0_WF_TMAC_TOP_DBGR6_DBGR6_MASK                       0xFFFFFFFF                // DBGR6[31..0]
#define BN0_WF_TMAC_TOP_DBGR6_DBGR6_SHFT                       0

/* =====================================================================================

  ---DBGR7 (0x820E4000 + 0x13C)---

    DBGR7[31..0]                 - (RO) Debug register (BN0 TXV4)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR7_DBGR7_ADDR                       BN0_WF_TMAC_TOP_DBGR7_ADDR
#define BN0_WF_TMAC_TOP_DBGR7_DBGR7_MASK                       0xFFFFFFFF                // DBGR7[31..0]
#define BN0_WF_TMAC_TOP_DBGR7_DBGR7_SHFT                       0

/* =====================================================================================

  ---DBGR8 (0x820E4000 + 0x140)---

    DBGR8[31..0]                 - (RO) Debug register (BN0 TXV5)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR8_DBGR8_ADDR                       BN0_WF_TMAC_TOP_DBGR8_ADDR
#define BN0_WF_TMAC_TOP_DBGR8_DBGR8_MASK                       0xFFFFFFFF                // DBGR8[31..0]
#define BN0_WF_TMAC_TOP_DBGR8_DBGR8_SHFT                       0

/* =====================================================================================

  ---DBGR9 (0x820E4000 + 0x144)---

    DBGR9[31..0]                 - (RO) Debug register (BN0 TXV6)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR9_DBGR9_ADDR                       BN0_WF_TMAC_TOP_DBGR9_ADDR
#define BN0_WF_TMAC_TOP_DBGR9_DBGR9_MASK                       0xFFFFFFFF                // DBGR9[31..0]
#define BN0_WF_TMAC_TOP_DBGR9_DBGR9_SHFT                       0

/* =====================================================================================

  ---DBGR10 (0x820E4000 + 0x148)---

    DBGR10[31..0]                - (RO) Debug register (BN0 TXV7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR10_DBGR10_ADDR                     BN0_WF_TMAC_TOP_DBGR10_ADDR
#define BN0_WF_TMAC_TOP_DBGR10_DBGR10_MASK                     0xFFFFFFFF                // DBGR10[31..0]
#define BN0_WF_TMAC_TOP_DBGR10_DBGR10_SHFT                     0

/* =====================================================================================

  ---DBGR11 (0x820E4000 + 0x14C)---

    DBGR11[31..0]                - (RO) Debug register (BN1 TXV1)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR11_DBGR11_ADDR                     BN0_WF_TMAC_TOP_DBGR11_ADDR
#define BN0_WF_TMAC_TOP_DBGR11_DBGR11_MASK                     0xFFFFFFFF                // DBGR11[31..0]
#define BN0_WF_TMAC_TOP_DBGR11_DBGR11_SHFT                     0

/* =====================================================================================

  ---DBGR12 (0x820E4000 + 0x150)---

    DBGR12[31..0]                - (RO) Debug register (BN1 TXV2)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR12_DBGR12_ADDR                     BN0_WF_TMAC_TOP_DBGR12_ADDR
#define BN0_WF_TMAC_TOP_DBGR12_DBGR12_MASK                     0xFFFFFFFF                // DBGR12[31..0]
#define BN0_WF_TMAC_TOP_DBGR12_DBGR12_SHFT                     0

/* =====================================================================================

  ---DBGR13 (0x820E4000 + 0x154)---

    DBGR13[31..0]                - (RO) Debug register (BN1 TXV3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR13_DBGR13_ADDR                     BN0_WF_TMAC_TOP_DBGR13_ADDR
#define BN0_WF_TMAC_TOP_DBGR13_DBGR13_MASK                     0xFFFFFFFF                // DBGR13[31..0]
#define BN0_WF_TMAC_TOP_DBGR13_DBGR13_SHFT                     0

/* =====================================================================================

  ---DBGR14 (0x820E4000 + 0x158)---

    DBGR14[31..0]                - (RO) Debug register (BN1 TXV4)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR14_DBGR14_ADDR                     BN0_WF_TMAC_TOP_DBGR14_ADDR
#define BN0_WF_TMAC_TOP_DBGR14_DBGR14_MASK                     0xFFFFFFFF                // DBGR14[31..0]
#define BN0_WF_TMAC_TOP_DBGR14_DBGR14_SHFT                     0

/* =====================================================================================

  ---DBGR15 (0x820E4000 + 0x15C)---

    DBGR15[31..0]                - (RO) Debug register (BN1 TXV5)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGR15_DBGR15_ADDR                     BN0_WF_TMAC_TOP_DBGR15_ADDR
#define BN0_WF_TMAC_TOP_DBGR15_DBGR15_MASK                     0xFFFFFFFF                // DBGR15[31..0]
#define BN0_WF_TMAC_TOP_DBGR15_DBGR15_SHFT                     0

/* =====================================================================================

  ---TFCR4 (0x820E4000 + 0x170)---

    BSSID2_BSR_AC0_TID[2..0]     - (RW) BSR AC0 to TID mapping table for BSSID2
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID2_BSR_AC1_TID[6..4]     - (RW) BSR AC1 to TID mapping table for BSSID2
    RESERVED7[7]                 - (RO) Reserved bits
    BSSID2_BSR_AC2_TID[10..8]    - (RW) BSR AC2 to TID mapping table for BSSID2
    RESERVED11[11]               - (RO) Reserved bits
    BSSID2_BSR_AC3_TID[14..12]   - (RW) BSR AC3 to TID mapping table for BSSID2
    RESERVED15[15]               - (RO) Reserved bits
    BSSID3_BSR_AC0_TID[18..16]   - (RW) BSR AC0 to TID mapping table for BSSID3
    RESERVED19[19]               - (RO) Reserved bits
    BSSID3_BSR_AC1_TID[22..20]   - (RW) BSR AC1 to TID mapping table for BSSID3
    RESERVED23[23]               - (RO) Reserved bits
    BSSID3_BSR_AC2_TID[26..24]   - (RW) BSR AC2 to TID mapping table for BSSID3
    RESERVED27[27]               - (RO) Reserved bits
    BSSID3_BSR_AC3_TID[30..28]   - (RW) BSR AC3 to TID mapping table for BSSID3
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC3_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC3_TID_MASK          0x70000000                // BSSID3_BSR_AC3_TID[30..28]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC3_TID_SHFT          28
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC2_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC2_TID_MASK          0x07000000                // BSSID3_BSR_AC2_TID[26..24]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC2_TID_SHFT          24
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC1_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC1_TID_MASK          0x00700000                // BSSID3_BSR_AC1_TID[22..20]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC1_TID_SHFT          20
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC0_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC0_TID_MASK          0x00070000                // BSSID3_BSR_AC0_TID[18..16]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID3_BSR_AC0_TID_SHFT          16
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC3_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC3_TID_MASK          0x00007000                // BSSID2_BSR_AC3_TID[14..12]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC3_TID_SHFT          12
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC2_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC2_TID_MASK          0x00000700                // BSSID2_BSR_AC2_TID[10..8]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC2_TID_SHFT          8
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC1_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC1_TID_MASK          0x00000070                // BSSID2_BSR_AC1_TID[6..4]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC1_TID_SHFT          4
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC0_TID_ADDR          BN0_WF_TMAC_TOP_TFCR4_ADDR
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC0_TID_MASK          0x00000007                // BSSID2_BSR_AC0_TID[2..0]
#define BN0_WF_TMAC_TOP_TFCR4_BSSID2_BSR_AC0_TID_SHFT          0

/* =====================================================================================

  ---TFCR5 (0x820E4000 + 0x174)---

    TFR_QN_SEQ_RANGE_IN_POWER2[3..0] - (RW) Specifies the sequence number range (in power of 2) for TF Response QoS_Null frame
                                     The maximum value should be limited to 12, i.e. the valid values are from 0 to 12.
                                     For example, if this vaule is set to 4, HW will adopt sequence number for QoS-NULL within the range
                                     (QN_INITIAL_SEQ,  (QN_INITIAL_SEQ+2^4-1) ).
    TFR_QN_INIT_SEQ[15..4]       - (RW) Initial sequence number for TF Response QoS_Null frame
    RESERVED16[30..16]           - (RO) Reserved bits
    TFR_QN_RESET_SEQ[31]         - (WO) Write 1 to reset the sequence number of TF Response QoS_Null frame to initial value.
                                     Writing 0 has no effect. Read always returns 0.

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_RESET_SEQ_ADDR            BN0_WF_TMAC_TOP_TFCR5_ADDR
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_RESET_SEQ_MASK            0x80000000                // TFR_QN_RESET_SEQ[31]
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_RESET_SEQ_SHFT            31
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_INIT_SEQ_ADDR             BN0_WF_TMAC_TOP_TFCR5_ADDR
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_INIT_SEQ_MASK             0x0000FFF0                // TFR_QN_INIT_SEQ[15..4]
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_INIT_SEQ_SHFT             4
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_SEQ_RANGE_IN_POWER2_ADDR  BN0_WF_TMAC_TOP_TFCR5_ADDR
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_SEQ_RANGE_IN_POWER2_MASK  0x0000000F                // TFR_QN_SEQ_RANGE_IN_POWER2[3..0]
#define BN0_WF_TMAC_TOP_TFCR5_TFR_QN_SEQ_RANGE_IN_POWER2_SHFT  0

/* =====================================================================================

  ---VHT_FP0CR (0x820E4000 + 0x178)---

    VHT_BW20_FRAME_POWER_MAX_DBM[7..0] - (RW) VHT BW 20 Maximum TX power dBm VHT_BW20_FRAME_POWER_MAX_DBM is applied
    VHT_BW40_FRAME_POWER_MAX_DBM[15..8] - (RW) VHT BW 40 Maximum TX power dBm 
                                     VHT_BW40_FRAME_POWER_MAX_DBM is applied
    VHT_BW80_FRAME_POWER_MAX_DBM[23..16] - (RW) VHT BW 80 Maximum TX power dBm 
                                     VHT_BW80_FRAME_POWER_MAX_DBM is applied
    VHT_BW160_FRAME_POWER_MAX_DBM[31..24] - (RW) VHT BW 160 Maximum TX power dBm VHT_BW160_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW160_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_VHT_FP0CR_ADDR
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW160_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // VHT_BW160_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW160_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW80_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_VHT_FP0CR_ADDR
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW80_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // VHT_BW80_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW80_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW40_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_VHT_FP0CR_ADDR
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW40_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // VHT_BW40_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW40_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW20_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_VHT_FP0CR_ADDR
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW20_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // VHT_BW20_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_VHT_FP0CR_VHT_BW20_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---THOCR (0x820E4000 + 0x17C)---

    THOCR_RSV1[12..0]            - (RW) Reserved, all 1s
    TX_MAX_LEN_CHK_EN_HENTB[13]  - (RW) the same as TX_MAX_LEN_CHK_EN_NHE
                                     (for HE non-TB PPDU)
    TX_MAX_LEN_CHK_EN_NHE[14]    - (RW) the maximum TX length is restricted by Max. APEP_Length
                                     (for Non-HE PPDU)
                                     0: No restriction
                                     1: enable restriction
    PAC_LEN_RECAL_EN[15]         - (RW) According to the NSYM & A-factor to re-calculate the max. available primary user length (for SW TX only)
                                     0: disable  re-calculation
                                     1: enable re-calculaton
    THOCR_RSV0[25..16]           - (RW) Reserved, all 0s
    RTSFAIL_ABORT_EN[26]         - (RW) When RTS-CTS sequence was failed, assert MAC TX ABORT
                                     0: Assert TX Data ABORT, reset data path only
                                     1: Assert MAC TX ABORT, reset data & control pathes
    BSR_VLD_WAIT_DIS[27]         - (RW) for BSR transmission, DON'T need to check BSR validation
                                     0: Need to wait
                                     1: DON'T need to wait
    SMPDU_BA_EN[28]              - (RW) 0: S-MPDY accept ACK response only
                                     1: S-MPDU accept ACK & BA response
    HETB_LEN_CHK_EN[29]          - (RW) Check the HETB TX Length
                                     0: disable checker
                                     1: enable checker
    NOACK_TX_CHK_DIS[30]         - (RW) Check the NoACK MPDU TX status
                                     0: disable checker
                                     1: enable checker
    TPC_VLD_WAIT_DIS[31]         - (RW) for Trigger frame transmission, DON'T need to wait for BBP's
                                     TPC_VLD
                                     0: Need to wait
                                     1: DON'T need to wait

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_THOCR_TPC_VLD_WAIT_DIS_ADDR            BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_TPC_VLD_WAIT_DIS_MASK            0x80000000                // TPC_VLD_WAIT_DIS[31]
#define BN0_WF_TMAC_TOP_THOCR_TPC_VLD_WAIT_DIS_SHFT            31
#define BN0_WF_TMAC_TOP_THOCR_NOACK_TX_CHK_DIS_ADDR            BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_NOACK_TX_CHK_DIS_MASK            0x40000000                // NOACK_TX_CHK_DIS[30]
#define BN0_WF_TMAC_TOP_THOCR_NOACK_TX_CHK_DIS_SHFT            30
#define BN0_WF_TMAC_TOP_THOCR_HETB_LEN_CHK_EN_ADDR             BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_HETB_LEN_CHK_EN_MASK             0x20000000                // HETB_LEN_CHK_EN[29]
#define BN0_WF_TMAC_TOP_THOCR_HETB_LEN_CHK_EN_SHFT             29
#define BN0_WF_TMAC_TOP_THOCR_SMPDU_BA_EN_ADDR                 BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_SMPDU_BA_EN_MASK                 0x10000000                // SMPDU_BA_EN[28]
#define BN0_WF_TMAC_TOP_THOCR_SMPDU_BA_EN_SHFT                 28
#define BN0_WF_TMAC_TOP_THOCR_BSR_VLD_WAIT_DIS_ADDR            BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_BSR_VLD_WAIT_DIS_MASK            0x08000000                // BSR_VLD_WAIT_DIS[27]
#define BN0_WF_TMAC_TOP_THOCR_BSR_VLD_WAIT_DIS_SHFT            27
#define BN0_WF_TMAC_TOP_THOCR_RTSFAIL_ABORT_EN_ADDR            BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_RTSFAIL_ABORT_EN_MASK            0x04000000                // RTSFAIL_ABORT_EN[26]
#define BN0_WF_TMAC_TOP_THOCR_RTSFAIL_ABORT_EN_SHFT            26
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV0_ADDR                  BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV0_MASK                  0x03FF0000                // THOCR_RSV0[25..16]
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV0_SHFT                  16
#define BN0_WF_TMAC_TOP_THOCR_PAC_LEN_RECAL_EN_ADDR            BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_PAC_LEN_RECAL_EN_MASK            0x00008000                // PAC_LEN_RECAL_EN[15]
#define BN0_WF_TMAC_TOP_THOCR_PAC_LEN_RECAL_EN_SHFT            15
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_NHE_ADDR       BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_NHE_MASK       0x00004000                // TX_MAX_LEN_CHK_EN_NHE[14]
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_NHE_SHFT       14
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_HENTB_ADDR     BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_HENTB_MASK     0x00002000                // TX_MAX_LEN_CHK_EN_HENTB[13]
#define BN0_WF_TMAC_TOP_THOCR_TX_MAX_LEN_CHK_EN_HENTB_SHFT     13
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV1_ADDR                  BN0_WF_TMAC_TOP_THOCR_ADDR
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV1_MASK                  0x00001FFF                // THOCR_RSV1[12..0]
#define BN0_WF_TMAC_TOP_THOCR_THOCR_RSV1_SHFT                  0

/* =====================================================================================

  ---SACR0 (0x820E4000 + 0x180)---

    FIX_ANT_ID[11..0]            - (RW) Fixed mode antenna ID for ANT0~3
                                     bit[2:0]: For TX0
                                     bit[5:3]: For TX1
                                     bit[8:6]: For TX2
                                     bit[11:9]: For TX3
    RESERVED12[25..12]           - (RO) Reserved bits
    RXEND_SWDLY_EN[26]           - (RW) Delays default antenna set switch time after RX frame is received
                                     1'b0: Disable; no delay
                                     1'b1: Enable
    CTS_ANT_SEL[27]              - (RW) Selects CTS's RX antenna
                                     1'b0: Follow RTS's TX antenna
                                     1'b1: Follow the protected data frame's TX antenna
    SANT_CCA_SRC_SEL[29..28]     - (RW) Selects primary channel CCA mode for smart antenna
                                     The definition is the same as TRCRx.BNx_CCA_SRC_SEL.
                                     The RX antenna switches default antenna set at CCA LOW only.
    SANT_FIX[30]                 - (RW) Smart antenna fixed mode
                                     1'b0: Default mode
                                     1'b1: Fixed mode
    SANT_EN[31]                  - (RW) Smart antenna control
                                     1'b0: Disable
                                     1'b1: Enable

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SACR0_SANT_EN_ADDR                     BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_SANT_EN_MASK                     0x80000000                // SANT_EN[31]
#define BN0_WF_TMAC_TOP_SACR0_SANT_EN_SHFT                     31
#define BN0_WF_TMAC_TOP_SACR0_SANT_FIX_ADDR                    BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_SANT_FIX_MASK                    0x40000000                // SANT_FIX[30]
#define BN0_WF_TMAC_TOP_SACR0_SANT_FIX_SHFT                    30
#define BN0_WF_TMAC_TOP_SACR0_SANT_CCA_SRC_SEL_ADDR            BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_SANT_CCA_SRC_SEL_MASK            0x30000000                // SANT_CCA_SRC_SEL[29..28]
#define BN0_WF_TMAC_TOP_SACR0_SANT_CCA_SRC_SEL_SHFT            28
#define BN0_WF_TMAC_TOP_SACR0_CTS_ANT_SEL_ADDR                 BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_CTS_ANT_SEL_MASK                 0x08000000                // CTS_ANT_SEL[27]
#define BN0_WF_TMAC_TOP_SACR0_CTS_ANT_SEL_SHFT                 27
#define BN0_WF_TMAC_TOP_SACR0_RXEND_SWDLY_EN_ADDR              BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_RXEND_SWDLY_EN_MASK              0x04000000                // RXEND_SWDLY_EN[26]
#define BN0_WF_TMAC_TOP_SACR0_RXEND_SWDLY_EN_SHFT              26
#define BN0_WF_TMAC_TOP_SACR0_FIX_ANT_ID_ADDR                  BN0_WF_TMAC_TOP_SACR0_ADDR
#define BN0_WF_TMAC_TOP_SACR0_FIX_ANT_ID_MASK                  0x00000FFF                // FIX_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_SACR0_FIX_ANT_ID_SHFT                  0

/* =====================================================================================

  ---SACR1 (0x820E4000 + 0x184)---

    OPT_ANT_ID[11..0]            - (RW) Optimial antenna ID for ANT0~3
                                     Same as FIX_ANT_ID
    RESERVED12[15..12]           - (RO) Reserved bits
    OMNI_ANT_ID[27..16]          - (RW) All directional antenna ID for ANT0~3
                                     Same as FIX_ANT_ID
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SACR1_OMNI_ANT_ID_ADDR                 BN0_WF_TMAC_TOP_SACR1_ADDR
#define BN0_WF_TMAC_TOP_SACR1_OMNI_ANT_ID_MASK                 0x0FFF0000                // OMNI_ANT_ID[27..16]
#define BN0_WF_TMAC_TOP_SACR1_OMNI_ANT_ID_SHFT                 16
#define BN0_WF_TMAC_TOP_SACR1_OPT_ANT_ID_ADDR                  BN0_WF_TMAC_TOP_SACR1_ADDR
#define BN0_WF_TMAC_TOP_SACR1_OPT_ANT_ID_MASK                  0x00000FFF                // OPT_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_SACR1_OPT_ANT_ID_SHFT                  0

/* =====================================================================================

  ---SACR2 (0x820E4000 + 0x188)---

    OMNI_ANT_DUTY[25..0]         - (RW) All directional antenna duty cycle
                                     Unit: 1us
    RESERVED26[27..26]           - (RO) Reserved bits
    TRTS_SWDLY[31..28]           - (RW) RTS->CTS antenna switch delay time
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SACR2_TRTS_SWDLY_ADDR                  BN0_WF_TMAC_TOP_SACR2_ADDR
#define BN0_WF_TMAC_TOP_SACR2_TRTS_SWDLY_MASK                  0xF0000000                // TRTS_SWDLY[31..28]
#define BN0_WF_TMAC_TOP_SACR2_TRTS_SWDLY_SHFT                  28
#define BN0_WF_TMAC_TOP_SACR2_OMNI_ANT_DUTY_ADDR               BN0_WF_TMAC_TOP_SACR2_ADDR
#define BN0_WF_TMAC_TOP_SACR2_OMNI_ANT_DUTY_MASK               0x03FFFFFF                // OMNI_ANT_DUTY[25..0]
#define BN0_WF_TMAC_TOP_SACR2_OMNI_ANT_DUTY_SHFT               0

/* =====================================================================================

  ---SACR3 (0x820E4000 + 0x18C)---

    OPT_ANT_DUTY[25..0]          - (RW) Optimal antenna duty cycle
                                     Unit: 1us
    RESERVED26[27..26]           - (RO) Reserved bits
    RXEND_SWDLY[31..28]          - (RW) RX end antenna switch delay
                                     Unit: 1us

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SACR3_RXEND_SWDLY_ADDR                 BN0_WF_TMAC_TOP_SACR3_ADDR
#define BN0_WF_TMAC_TOP_SACR3_RXEND_SWDLY_MASK                 0xF0000000                // RXEND_SWDLY[31..28]
#define BN0_WF_TMAC_TOP_SACR3_RXEND_SWDLY_SHFT                 28
#define BN0_WF_TMAC_TOP_SACR3_OPT_ANT_DUTY_ADDR                BN0_WF_TMAC_TOP_SACR3_ADDR
#define BN0_WF_TMAC_TOP_SACR3_OPT_ANT_DUTY_MASK                0x03FFFFFF                // OPT_ANT_DUTY[25..0]
#define BN0_WF_TMAC_TOP_SACR3_OPT_ANT_DUTY_SHFT                0

/* =====================================================================================

  ---TWCR0 (0x820E4000 + 0x194)---

    MACPHY_IF_WDT_EXTOUT[7..0]   - (RW) MAC-PHY interface watch dog extra timeout time (unit: 64us)
                                     the total timeout time is (Packet's TXTime + Extra Timeout Time)
                                     0: means NO extra timeouot time
    MACPHY_IF_WDT_EN[8]          - (RW) MAC-PHY interface watch dog timer enable control
                                     0: disable WDT
                                     1: enable WDT
    TWCR0_RSV0[31..9]            - (RW) for Trigger frame transmission, DON'T need to wait for BBP's
                                     TPC_VLD
                                     0: Need to wait
                                     1: DON'T need to wait

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TWCR0_TWCR0_RSV0_ADDR                  BN0_WF_TMAC_TOP_TWCR0_ADDR
#define BN0_WF_TMAC_TOP_TWCR0_TWCR0_RSV0_MASK                  0xFFFFFE00                // TWCR0_RSV0[31..9]
#define BN0_WF_TMAC_TOP_TWCR0_TWCR0_RSV0_SHFT                  9
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EN_ADDR            BN0_WF_TMAC_TOP_TWCR0_ADDR
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EN_MASK            0x00000100                // MACPHY_IF_WDT_EN[8]
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EN_SHFT            8
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EXTOUT_ADDR        BN0_WF_TMAC_TOP_TWCR0_ADDR
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EXTOUT_MASK        0x000000FF                // MACPHY_IF_WDT_EXTOUT[7..0]
#define BN0_WF_TMAC_TOP_TWCR0_MACPHY_IF_WDT_EXTOUT_SHFT        0

/* =====================================================================================

  ---SACR6 (0x820E4000 + 0x198)---

    CURR_ANT[11..0]              - (RO) Current antenna ID for ANT0~3
    CURR_ANT_H[23..12]           - (RO) Current antenna ID for ANT4~7
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_H_ADDR                  BN0_WF_TMAC_TOP_SACR6_ADDR
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_H_MASK                  0x00FFF000                // CURR_ANT_H[23..12]
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_H_SHFT                  12
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_ADDR                    BN0_WF_TMAC_TOP_SACR6_ADDR
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_MASK                    0x00000FFF                // CURR_ANT[11..0]
#define BN0_WF_TMAC_TOP_SACR6_CURR_ANT_SHFT                    0

/* =====================================================================================

  ---DBGCTRL (0x820E4000 + 0x19C)---

    DBGCTRL_RSV0[9..0]           - (RW) Reserved
    COEX_UPH_CNT_EN[10]          - (RW) FDD COEX "force UPH to 0" event count enable
                                     0: disable
                                     1: enable
    COEX_UPH_CNT_MODE[11]        - (RW) FDD COEX "force UPH to 0" event count clear mode
                                     0: write 0 to clear
                                     1: read clear
    DBG_FLAG_SWAP_EN[15..12]     - (RW) Swap the debug flag
    DBG_UX_SEL[22..16]           - (RW) Selects TX path
    DBG_TFSM_PAGE[23]            - (RW) Select the TFSM debug flag page
    DBG_BYTE_SEL[26..24]         - (RW) Selects debug byte of bus signals
                                     2'b00: bit[7:0]
                                     2'b01: bit[15:8]
                                     and so on
    RESERVED27[27]               - (RO) Reserved bits
    DBG_TXV_SEL[30..28]          - (RW) TXV Capture filter mode
                                     3'h0: all packets
                                     3'h1: SW TX
                                     3'h2: response packet
                                     3'h3: protection packet
                                     3'h4: trigger response packet
                                     3'h5: response for basic trigger
                                     Others: reserved
    ERR_IND_CLR[31]              - (RW) Clears error indicator status
                                     1'b0: Not clear
                                     1'b1: Clear

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DBGCTRL_ERR_IND_CLR_ADDR               BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_ERR_IND_CLR_MASK               0x80000000                // ERR_IND_CLR[31]
#define BN0_WF_TMAC_TOP_DBGCTRL_ERR_IND_CLR_SHFT               31
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TXV_SEL_ADDR               BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TXV_SEL_MASK               0x70000000                // DBG_TXV_SEL[30..28]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TXV_SEL_SHFT               28
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_BYTE_SEL_ADDR              BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_BYTE_SEL_MASK              0x07000000                // DBG_BYTE_SEL[26..24]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_BYTE_SEL_SHFT              24
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TFSM_PAGE_ADDR             BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TFSM_PAGE_MASK             0x00800000                // DBG_TFSM_PAGE[23]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_TFSM_PAGE_SHFT             23
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_UX_SEL_ADDR                BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_UX_SEL_MASK                0x007F0000                // DBG_UX_SEL[22..16]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_UX_SEL_SHFT                16
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_FLAG_SWAP_EN_ADDR          BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_FLAG_SWAP_EN_MASK          0x0000F000                // DBG_FLAG_SWAP_EN[15..12]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBG_FLAG_SWAP_EN_SHFT          12
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_MODE_ADDR         BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_MODE_MASK         0x00000800                // COEX_UPH_CNT_MODE[11]
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_MODE_SHFT         11
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_EN_ADDR           BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_EN_MASK           0x00000400                // COEX_UPH_CNT_EN[10]
#define BN0_WF_TMAC_TOP_DBGCTRL_COEX_UPH_CNT_EN_SHFT           10
#define BN0_WF_TMAC_TOP_DBGCTRL_DBGCTRL_RSV0_ADDR              BN0_WF_TMAC_TOP_DBGCTRL_ADDR
#define BN0_WF_TMAC_TOP_DBGCTRL_DBGCTRL_RSV0_MASK              0x000003FF                // DBGCTRL_RSV0[9..0]
#define BN0_WF_TMAC_TOP_DBGCTRL_DBGCTRL_RSV0_SHFT              0

/* =====================================================================================

  ---DSWCR00 (0x820E4000 + 0x1A0)---

    DSW_PEER_MAC_b47b32[15..0]   - (RW) Peer MAC address bit47 to bit32 by SW to locate peer unicast packets
    DSW_CNT_RST[20..16]          - (WO) Write 1 to clear the related counter. Read always return 0.
                                     bit[0]: reset DSW_RTS_OVERFLOW_CNT
                                     bit[1]: reset DSW_DATA_OVERFLOW_CNT
                                     bit[2]: reset DWS_AIRCONDITION_FAIL_CNT
                                     bit[3]: reset DWS_PREDEFINE_FAIL_CNT
                                     bit[4]: reset other counters
    DSW0_RSVD2[23..21]           - (RW) Reserved
    DSW_MV_AVG_WEIGHT[26..24]    - (RW) The moving average weighting for new coming MEASURE_SIZE
                                     3'h0 : 1
                                     3'h1 : 1/2
                                     3'h2 : 1/4
                                     3'h3 : 1/8
                                     3'h4 : 1/16
                                     3'h5 : 1/32
                                     3'h6 : 1/64
                                     3'h7 : 1/128
    DSW0_RSVD1[29..27]           - (RW) Reserved
    DSW_MODE_SEL[31..30]         - (RW) Select dynamic silence window mode
                                     2'h0 : Disable measuring.
                                     2'h1 : Measure by BA/ACK responding time.
                                     2'h2 : Measure by peer traffic receiving time.
                                     2'h3 : Reserved

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MODE_SEL_ADDR              BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MODE_SEL_MASK              0xC0000000                // DSW_MODE_SEL[31..30]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MODE_SEL_SHFT              30
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD1_ADDR                BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD1_MASK                0x38000000                // DSW0_RSVD1[29..27]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD1_SHFT                27
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MV_AVG_WEIGHT_ADDR         BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MV_AVG_WEIGHT_MASK         0x07000000                // DSW_MV_AVG_WEIGHT[26..24]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_MV_AVG_WEIGHT_SHFT         24
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD2_ADDR                BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD2_MASK                0x00E00000                // DSW0_RSVD2[23..21]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW0_RSVD2_SHFT                21
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_CNT_RST_ADDR               BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_CNT_RST_MASK               0x001F0000                // DSW_CNT_RST[20..16]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_CNT_RST_SHFT               16
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_PEER_MAC_b47b32_ADDR       BN0_WF_TMAC_TOP_DSWCR00_ADDR
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_PEER_MAC_b47b32_MASK       0x0000FFFF                // DSW_PEER_MAC_b47b32[15..0]
#define BN0_WF_TMAC_TOP_DSWCR00_DSW_PEER_MAC_b47b32_SHFT       0

/* =====================================================================================

  ---DSWCR01 (0x820E4000 + 0x1A4)---

    DSW_PEER_MAC_b31b0[31..0]    - (RW) Peer MAC address bit31 to bit0 by SW to locate peer unicast packets
                                     (for COEX)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR01_DSW_PEER_MAC_b31b0_ADDR        BN0_WF_TMAC_TOP_DSWCR01_ADDR
#define BN0_WF_TMAC_TOP_DSWCR01_DSW_PEER_MAC_b31b0_MASK        0xFFFFFFFF                // DSW_PEER_MAC_b31b0[31..0]
#define BN0_WF_TMAC_TOP_DSWCR01_DSW_PEER_MAC_b31b0_SHFT        0

/* =====================================================================================

  ---DSWCR02 (0x820E4000 + 0x1A8)---

    DSW_PREFACE_ACK_SIZE[15..0]  - (RO) How much time need to spend after receiving the final ACK for null frame with power save bit = 1 (Tp)
                                     
                                     Note: This register is reset to 0 each time at T0 automatically. SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually
    DSW_PREFACE_SIZE[31..16]     - (RO) How much time need to spend before sending the first null frame with power save bit = 1 (Tp)
                                     
                                     Note: This register is reset to 0 each time at T0 automatically. SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_SIZE_ADDR          BN0_WF_TMAC_TOP_DSWCR02_ADDR
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_SIZE_MASK          0xFFFF0000                // DSW_PREFACE_SIZE[31..16]
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_SIZE_SHFT          16
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_ACK_SIZE_ADDR      BN0_WF_TMAC_TOP_DSWCR02_ADDR
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_ACK_SIZE_MASK      0x0000FFFF                // DSW_PREFACE_ACK_SIZE[15..0]
#define BN0_WF_TMAC_TOP_DSWCR02_DSW_PREFACE_ACK_SIZE_SHFT      0

/* =====================================================================================

  ---DSWCR03 (0x820E4000 + 0x1AC)---

    DSW_PREFACE_ACK_MIN_SIZE[15..0] - (RO) The minimum PREFACE_ACK_SIZE of all cumulative moving average
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[4] to reset to all 1s manually
    DSW_PREFACE_ACK_MAX_SIZE[31..16] - (RO) The maximum PREFACE_ACK_SIZE of all cumulative measurement.
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MAX_SIZE_ADDR  BN0_WF_TMAC_TOP_DSWCR03_ADDR
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MAX_SIZE_MASK  0xFFFF0000                // DSW_PREFACE_ACK_MAX_SIZE[31..16]
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MAX_SIZE_SHFT  16
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MIN_SIZE_ADDR  BN0_WF_TMAC_TOP_DSWCR03_ADDR
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MIN_SIZE_MASK  0x0000FFFF                // DSW_PREFACE_ACK_MIN_SIZE[15..0]
#define BN0_WF_TMAC_TOP_DSWCR03_DSW_PREFACE_ACK_MIN_SIZE_SHFT  0

/* =====================================================================================

  ---DSWCR04 (0x820E4000 + 0x1B0)---

    DSW_MV_AVG_SIZE[15..0]       - (RW) Cumulative moving average of all MEASURE_SIZE. MAC regards T measured between T0 to TE as a new transaction occurs.
                                     
                                     Note: SW can write initial value to this counter. SW can also write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually
    DSW_MEASURE_SIZE[31..16]     - (RO) The longest period need to wait until received no unicast packets from peer. This register would be overwritten from T1 to Tn until local timer reaches TE.
                                     
                                     Note: This register is reset to 0 each time at T0 automatically. SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MEASURE_SIZE_ADDR          BN0_WF_TMAC_TOP_DSWCR04_ADDR
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MEASURE_SIZE_MASK          0xFFFF0000                // DSW_MEASURE_SIZE[31..16]
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MEASURE_SIZE_SHFT          16
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MV_AVG_SIZE_ADDR           BN0_WF_TMAC_TOP_DSWCR04_ADDR
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MV_AVG_SIZE_MASK           0x0000FFFF                // DSW_MV_AVG_SIZE[15..0]
#define BN0_WF_TMAC_TOP_DSWCR04_DSW_MV_AVG_SIZE_SHFT           0

/* =====================================================================================

  ---DSWCR05 (0x820E4000 + 0x1B4)---

    DSW_MV_MIN_SIZE[15..0]       - (RO) The minimum MEASURE_SIZE of all cumulative moving average
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[4] to reset to all 1s manually
    DSW_MV_MAX_SIZE[31..16]      - (RO) The maximum MEASURE_SIZE of all cumulative moving average
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MAX_SIZE_ADDR           BN0_WF_TMAC_TOP_DSWCR05_ADDR
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MAX_SIZE_MASK           0xFFFF0000                // DSW_MV_MAX_SIZE[31..16]
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MAX_SIZE_SHFT           16
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MIN_SIZE_ADDR           BN0_WF_TMAC_TOP_DSWCR05_ADDR
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MIN_SIZE_MASK           0x0000FFFF                // DSW_MV_MIN_SIZE[15..0]
#define BN0_WF_TMAC_TOP_DSWCR05_DSW_MV_MIN_SIZE_SHFT           0

/* =====================================================================================

  ---DSWCR06 (0x820E4000 + 0x1B8)---

    DSW_ACK_CNT[7..0]            - (RO) How many ACK/BA NIC response to peer unicast packets. This register does not count other data packets.
                                     
                                     Note: This register is reset to 0 each time at T0 automatically. SW can write 1 to DSW_CNT_RST.bit[4] to reset to 0 manually
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR06_DSW_ACK_CNT_ADDR               BN0_WF_TMAC_TOP_DSWCR06_ADDR
#define BN0_WF_TMAC_TOP_DSWCR06_DSW_ACK_CNT_MASK               0x000000FF                // DSW_ACK_CNT[7..0]
#define BN0_WF_TMAC_TOP_DSWCR06_DSW_ACK_CNT_SHFT               0

/* =====================================================================================

  ---DSWCR07 (0x820E4000 + 0x1BC)---

    DSW_RTS_OVERFLOW_CNT[7..0]   - (RO) If MAC parses receiving RTS frames and find their source address is equal to rSL_PEER_MAC, it will increase
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[0] to reset to 0 manually
    DSW_DATA_OVERFLOW_CNT[15..8] - (RO) If MAC parses receiving data frames and find their source address is equal to rSL_PEER_MAC, it will increase
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[1] to reset to 0 manually
    DWS_AIRCONDITION_FAIL_CNT[23..16] - (RO) If NIC cannot send the null frame within predetermined silence window (TS - T0 >= predetermined silence window), it will increase
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[2] to reset to 0 manually
                                     (for COEX)
    DWS_PREDEFINE_FAIL_CNT[31..24] - (RO) If NIC detect the end time of  RX of peer packets over TE or NIC TX time which need to response peer with ACK/BA is over TE, it will increase. For each transmission between NIC and peer, this counter adds once to indicate it
                                     
                                     Note: SW can write 1 to DSW_CNT_RST.bit[3] to reset to 0 manually

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_PREDEFINE_FAIL_CNT_ADDR    BN0_WF_TMAC_TOP_DSWCR07_ADDR
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_PREDEFINE_FAIL_CNT_MASK    0xFF000000                // DWS_PREDEFINE_FAIL_CNT[31..24]
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_PREDEFINE_FAIL_CNT_SHFT    24
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_AIRCONDITION_FAIL_CNT_ADDR BN0_WF_TMAC_TOP_DSWCR07_ADDR
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_AIRCONDITION_FAIL_CNT_MASK 0x00FF0000                // DWS_AIRCONDITION_FAIL_CNT[23..16]
#define BN0_WF_TMAC_TOP_DSWCR07_DWS_AIRCONDITION_FAIL_CNT_SHFT 16
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_DATA_OVERFLOW_CNT_ADDR     BN0_WF_TMAC_TOP_DSWCR07_ADDR
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_DATA_OVERFLOW_CNT_MASK     0x0000FF00                // DSW_DATA_OVERFLOW_CNT[15..8]
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_DATA_OVERFLOW_CNT_SHFT     8
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_RTS_OVERFLOW_CNT_ADDR      BN0_WF_TMAC_TOP_DSWCR07_ADDR
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_RTS_OVERFLOW_CNT_MASK      0x000000FF                // DSW_RTS_OVERFLOW_CNT[7..0]
#define BN0_WF_TMAC_TOP_DSWCR07_DSW_RTS_OVERFLOW_CNT_SHFT      0

/* =====================================================================================

  ---PPDR1 (0x820E4000 + 0x1C0)---

    DDLMT_DLY_OFST_HE80_NSS1[7..0] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE80_NSS2[15..8] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE80_NSS3[23..16] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE80_NSS4[31..24] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS4_ADDR    BN0_WF_TMAC_TOP_PPDR1_ADDR
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS4_MASK    0xFF000000                // DDLMT_DLY_OFST_HE80_NSS4[31..24]
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS4_SHFT    24
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS3_ADDR    BN0_WF_TMAC_TOP_PPDR1_ADDR
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS3_MASK    0x00FF0000                // DDLMT_DLY_OFST_HE80_NSS3[23..16]
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS3_SHFT    16
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS2_ADDR    BN0_WF_TMAC_TOP_PPDR1_ADDR
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS2_MASK    0x0000FF00                // DDLMT_DLY_OFST_HE80_NSS2[15..8]
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS2_SHFT    8
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS1_ADDR    BN0_WF_TMAC_TOP_PPDR1_ADDR
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS1_MASK    0x000000FF                // DDLMT_DLY_OFST_HE80_NSS1[7..0]
#define BN0_WF_TMAC_TOP_PPDR1_DDLMT_DLY_OFST_HE80_NSS1_SHFT    0

/* =====================================================================================

  ---PPDR3 (0x820E4000 + 0x1C8)---

    DDLMT_DLY_OFST_HE160_NSS1[7..0] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE160_NSS2[15..8] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE160_NSS3[23..16] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)
    DDLMT_DLY_OFST_HE160_NSS4[31..24] - (RW) Delay control for TMAC to insert zero-length delimiter when TX packet is not ready
                                     Unit: 0.4us/0.8us/1.6us (NC/HC/QC mode)
                                     Note: Before updating this field, MAC TX must be disabled.
                                     (ARB.SCR.MAC_TX_DIS)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS4_ADDR   BN0_WF_TMAC_TOP_PPDR3_ADDR
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS4_MASK   0xFF000000                // DDLMT_DLY_OFST_HE160_NSS4[31..24]
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS4_SHFT   24
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS3_ADDR   BN0_WF_TMAC_TOP_PPDR3_ADDR
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS3_MASK   0x00FF0000                // DDLMT_DLY_OFST_HE160_NSS3[23..16]
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS3_SHFT   16
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS2_ADDR   BN0_WF_TMAC_TOP_PPDR3_ADDR
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS2_MASK   0x0000FF00                // DDLMT_DLY_OFST_HE160_NSS2[15..8]
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS2_SHFT   8
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS1_ADDR   BN0_WF_TMAC_TOP_PPDR3_ADDR
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS1_MASK   0x000000FF                // DDLMT_DLY_OFST_HE160_NSS1[7..0]
#define BN0_WF_TMAC_TOP_PPDR3_DDLMT_DLY_OFST_HE160_NSS1_SHFT   0

/* =====================================================================================

  ---TFCR0 (0x820E4000 + 0x1E0)---

    HETB_SPE_IDX[4..0]           - (RW) ignore the trigger frame's CS requirement bit
                                     0: follow CS requirement bit
                                     1: ignore CS requirement bit and doesn't perform CS detection
    RESERVED5[7..5]              - (RO) Reserved bits
    SW_BQR[15..8]                - (RW) The BQR response for SW mode
                                     bit is 1, means related sub-channel is IDLE
                                     bit is 0, means related sub-channel is BUSY or Unavailable
    PRIM20M_CH[18..16]           - (RW) Primary 20MHz sub-channel index
                                     3'h0: primary 20MHz is in lowest frequency
                                     3'h7: primary 20MHz is in highest frequency
    CBW_160NC_IND[19]            - (RW) indicate 160MHz CBW is 160NC
                                     0: 160MHz CBW is 160C
                                     1: 160MHz CBW is 160NC
                                     Note: if CBW is less than 160MHz, this bit should be set to 0
    STA_CBW_MODE[21..20]         - (RW) indicate the STA CBW Mode
                                     00: the STA is a normal STA
                                     01: the STA is a 20MHz only STA (AGG_CR.RF_BW should be 20MHz)
                                     10: the STA is an 80MHz only STA (AGG_CR.RF_BW should be 80MHz)
                                     others: reserved
    TFR_FORCE_NOBF[22]           - (RW) Force Trigger Response frame without BF
                                     0: no force, follow original BF control
                                     1: force to NO BF
    RESERVED23[23]               - (RO) Reserved bits
    RSSI_AVG_ALL[24]             - (RW) Average all valid 20MHz sub-channel RSSI
                                     0: enable
                                     1: enable
    RSSI_AVG_FORCE20[25]         - (RW) Use primary 20MHz RSSI as RSSI average value
                                     0: enable
                                     1: enable
    ACTIVE_BSR_EN[26]            - (RW) Acive BSR mode enable
                                     0: Does NOT report BSR in Non-HE_TB QoS Data frame
                                     1: Report BSR in Non-HE_TB QoS Data frame
    TF_CXD_EN[27]                - (RW) Cascade Trigger sequence enable
                                     0: Not support cascade trigger sequence
                                     1: support cascade trigger sequence
    TF_BFR_CHK_EN[28]            - (RW) Check if the BFR TX request wzs asserted before TXV Timeout
                                     0: doesn't check
                                     1: perform check and abort the BFR TX if BFR TX request was NOT asserted beofred TXV Timeout
    TF_CSR_MODE[29]              - (RW) Response mode for Trigger frame CS requirement
                                     0: follow CS requirement bit and detect RU related sub-channel ED-CCA
                                     1: ignore CS requirement bit and doesn't perform CS detection
    BQR_MODE[30]                 - (RW) BQR response mode
                                     0: Hybrid mode, (sub-channel IDLE status & SW_BQR)
                                     1: SW mode, MAC response BQR according to SW_BQR field
    BSR_MODE[31]                 - (RW) BSR response mode
                                     0: transmit only one NoACK QoS_NULL frame
                                     1: transmit multiple NoACK QoS_NULL frames

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR0_BSR_MODE_ADDR                    BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_BSR_MODE_MASK                    0x80000000                // BSR_MODE[31]
#define BN0_WF_TMAC_TOP_TFCR0_BSR_MODE_SHFT                    31
#define BN0_WF_TMAC_TOP_TFCR0_BQR_MODE_ADDR                    BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_BQR_MODE_MASK                    0x40000000                // BQR_MODE[30]
#define BN0_WF_TMAC_TOP_TFCR0_BQR_MODE_SHFT                    30
#define BN0_WF_TMAC_TOP_TFCR0_TF_CSR_MODE_ADDR                 BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_TF_CSR_MODE_MASK                 0x20000000                // TF_CSR_MODE[29]
#define BN0_WF_TMAC_TOP_TFCR0_TF_CSR_MODE_SHFT                 29
#define BN0_WF_TMAC_TOP_TFCR0_TF_BFR_CHK_EN_ADDR               BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_TF_BFR_CHK_EN_MASK               0x10000000                // TF_BFR_CHK_EN[28]
#define BN0_WF_TMAC_TOP_TFCR0_TF_BFR_CHK_EN_SHFT               28
#define BN0_WF_TMAC_TOP_TFCR0_TF_CXD_EN_ADDR                   BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_TF_CXD_EN_MASK                   0x08000000                // TF_CXD_EN[27]
#define BN0_WF_TMAC_TOP_TFCR0_TF_CXD_EN_SHFT                   27
#define BN0_WF_TMAC_TOP_TFCR0_ACTIVE_BSR_EN_ADDR               BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_ACTIVE_BSR_EN_MASK               0x04000000                // ACTIVE_BSR_EN[26]
#define BN0_WF_TMAC_TOP_TFCR0_ACTIVE_BSR_EN_SHFT               26
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_FORCE20_ADDR            BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_FORCE20_MASK            0x02000000                // RSSI_AVG_FORCE20[25]
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_FORCE20_SHFT            25
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_ALL_ADDR                BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_ALL_MASK                0x01000000                // RSSI_AVG_ALL[24]
#define BN0_WF_TMAC_TOP_TFCR0_RSSI_AVG_ALL_SHFT                24
#define BN0_WF_TMAC_TOP_TFCR0_TFR_FORCE_NOBF_ADDR              BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_TFR_FORCE_NOBF_MASK              0x00400000                // TFR_FORCE_NOBF[22]
#define BN0_WF_TMAC_TOP_TFCR0_TFR_FORCE_NOBF_SHFT              22
#define BN0_WF_TMAC_TOP_TFCR0_STA_CBW_MODE_ADDR                BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_STA_CBW_MODE_MASK                0x00300000                // STA_CBW_MODE[21..20]
#define BN0_WF_TMAC_TOP_TFCR0_STA_CBW_MODE_SHFT                20
#define BN0_WF_TMAC_TOP_TFCR0_CBW_160NC_IND_ADDR               BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_CBW_160NC_IND_MASK               0x00080000                // CBW_160NC_IND[19]
#define BN0_WF_TMAC_TOP_TFCR0_CBW_160NC_IND_SHFT               19
#define BN0_WF_TMAC_TOP_TFCR0_PRIM20M_CH_ADDR                  BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_PRIM20M_CH_MASK                  0x00070000                // PRIM20M_CH[18..16]
#define BN0_WF_TMAC_TOP_TFCR0_PRIM20M_CH_SHFT                  16
#define BN0_WF_TMAC_TOP_TFCR0_SW_BQR_ADDR                      BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_SW_BQR_MASK                      0x0000FF00                // SW_BQR[15..8]
#define BN0_WF_TMAC_TOP_TFCR0_SW_BQR_SHFT                      8
#define BN0_WF_TMAC_TOP_TFCR0_HETB_SPE_IDX_ADDR                BN0_WF_TMAC_TOP_TFCR0_ADDR
#define BN0_WF_TMAC_TOP_TFCR0_HETB_SPE_IDX_MASK                0x0000001F                // HETB_SPE_IDX[4..0]
#define BN0_WF_TMAC_TOP_TFCR0_HETB_SPE_IDX_SHFT                0

/* =====================================================================================

  ---THOCR1 (0x820E4000 + 0x1E4)---

    TX_CCA_DLY_TOUT[3..0]        - (RW) TX delay by ED-CCA timeout time
                                     Use Scenario : ED-CCA was asserted during TX starting period
                                     (unit is 0.8us/1.6us/3.2us for NC/HC/QC, maximum value is 15*unit us)
                                     0: NO delay
                                     1: max. delay time is 1*unit us
                                     2. max. delay time is 2*unit us
                                     and so on
    TX_RSP_DLY_TOUT[7..4]        - (RW) TX Response delay timeout time
                                     Use Scenario : RX packet to TX response frame, except RX trigger frame
                                     the same as  TX_CCA_DLY_TOUT
    TX_BST_DLY_TOUT[11..8]       - (RW) TXOP burst delay timeout time
                                     Use Scanario : RX response frame to TX next packet
                                     the same as  TX_CCA_DLY_TOUT
    THOCR1_RSV1[15..12]          - (RW) for Trigger frame transmission, DON'T need to wait for BBP's
                                     TPC_VLD
                                     0: Need to wait
                                     1: DON'T need to wait
    TX_DLY_EN[18..16]            - (RW) TX delay function enable control
                                     bit[2]: TX_BST_DLY_EN
                                     bit[1]: TX_RSP_DLY_EN
                                     bit[0]: TX_CCA_DLY_EN
                                     0: disable related delay funciton
                                     1: enable related delay function
    THOCR1_RSV0[31..19]          - (RW) for Trigger frame transmission, DON'T need to wait for BBP's
                                     TPC_VLD
                                     0: Need to wait
                                     1: DON'T need to wait

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV0_ADDR                BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV0_MASK                0xFFF80000                // THOCR1_RSV0[31..19]
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV0_SHFT                19
#define BN0_WF_TMAC_TOP_THOCR1_TX_DLY_EN_ADDR                  BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_TX_DLY_EN_MASK                  0x00070000                // TX_DLY_EN[18..16]
#define BN0_WF_TMAC_TOP_THOCR1_TX_DLY_EN_SHFT                  16
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV1_ADDR                BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV1_MASK                0x0000F000                // THOCR1_RSV1[15..12]
#define BN0_WF_TMAC_TOP_THOCR1_THOCR1_RSV1_SHFT                12
#define BN0_WF_TMAC_TOP_THOCR1_TX_BST_DLY_TOUT_ADDR            BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_TX_BST_DLY_TOUT_MASK            0x00000F00                // TX_BST_DLY_TOUT[11..8]
#define BN0_WF_TMAC_TOP_THOCR1_TX_BST_DLY_TOUT_SHFT            8
#define BN0_WF_TMAC_TOP_THOCR1_TX_RSP_DLY_TOUT_ADDR            BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_TX_RSP_DLY_TOUT_MASK            0x000000F0                // TX_RSP_DLY_TOUT[7..4]
#define BN0_WF_TMAC_TOP_THOCR1_TX_RSP_DLY_TOUT_SHFT            4
#define BN0_WF_TMAC_TOP_THOCR1_TX_CCA_DLY_TOUT_ADDR            BN0_WF_TMAC_TOP_THOCR1_ADDR
#define BN0_WF_TMAC_TOP_THOCR1_TX_CCA_DLY_TOUT_MASK            0x0000000F                // TX_CCA_DLY_TOUT[3..0]
#define BN0_WF_TMAC_TOP_THOCR1_TX_CCA_DLY_TOUT_SHFT            0

/* =====================================================================================

  ---TFCR2 (0x820E4000 + 0x1E8)---

    TRIG_HELTF_TYPE_0[1..0]      - (RW) HELTF type Mapping for TRIG.GI_LTF_TYPE = 0
                                     00: 1x HE_LTF for 3.2us
                                     01: 2x HE_LTF for 6.4us
                                     10: 4x HE_LTF for 12.8us
                                     11: Reserved
    TRIG_HELTF_TYPE_1[3..2]      - (RW) HELTF type Mapping for TRIG.GI_LTF_TYPE = 1
                                     the same as TRIG_HELTF_TYPE_0
    TRIG_HELTF_TYPE_2[5..4]      - (RW) HELTF type Mapping for TRIG.GI_LTF_TYPE = 2
                                     the same as TRIG_HELTF_TYPE_0
    TRIG_HELTF_TYPE_3[7..6]      - (RW) HELTF type Mapping for TRIG.GI_LTF_TYPE = 3
                                     the same as TRIG_HELTF_TYPE_0
    TRIG_GI_TYPE_0[9..8]         - (RW) GI type Mapping for TRIG.GI_LTF_TYPE = 0
                                     00: GI is 0.8us
                                     01: GI is 1.6us
                                     10: GI is 3.2us
                                     11: Reserved
    TRIG_GI_TYPE_1[11..10]       - (RW) GI type Mapping for TRIG.GI_LTF_TYPE = 1
                                     the same as TRIG_GI_TYPE_0
    TRIG_GI_TYPE_2[13..12]       - (RW) GI type Mapping for TRIG.GI_LTF_TYPE = 2
                                     the same as TRIG_GI_TYPE_0
    TRIG_GI_TYPE_3[15..14]       - (RW) GI type Mapping for TRIG.GI_LTF_TYPE = 3
                                     the same as TRIG_GI_TYPE_0
    RESERVED16[19..16]           - (RO) Reserved bits
    BSSID00_ACTRL_PAD_SEL[20]    - (RW) A-Control padding selection for BSSID00
                                     0: pad all 0s
                                     1: pad all 1s
    BSSID01_ACTRL_PAD_SEL[21]    - (RW) A-Control padding selection for BSSID01
                                     the same as BSSID00_ACTRL_PAD_SEL
    BSSID02_ACTRL_PAD_SEL[22]    - (RW) A-Control padding selection for BSSID02
                                     the same as BSSID00_ACTRL_PAD_SEL
    BSSID03_ACTRL_PAD_SEL[23]    - (RW) A-Control padding selection for BSSID03
                                     tha same as BSSID00_ACTRL_PAD_SEL
    BSSID00_TFR_DIS_CTRL[25..24] - (RW) Trigger Response Disable Control (for BSSID00)
                                     00: can response control frame and UL trigger date
                                     01: can response control frame, but should NOT response UL trigger data
                                     10: No response
                                     11: reserved (No response)
    BSSID01_TFR_DIS_CTRL[27..26] - (RW) Trigger Response Disable Control (for BSSID01)
                                     the same as BSSID0_TFR_DIS_CTRL
    BSSID02_TFR_DIS_CTRL[29..28] - (RW) Trigger Response Disable Control (for BSSID02)
                                     the same as BSSID0_TFR_DIS_CTRL
    BSSID03_TFR_DIS_CTRL[31..30] - (RW) Trigger Response Disable Control (for BSSID03)
                                     the same as BSSID0_TFR_DIS_CTRL

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_TFR_DIS_CTRL_ADDR        BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_TFR_DIS_CTRL_MASK        0xC0000000                // BSSID03_TFR_DIS_CTRL[31..30]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_TFR_DIS_CTRL_SHFT        30
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_TFR_DIS_CTRL_ADDR        BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_TFR_DIS_CTRL_MASK        0x30000000                // BSSID02_TFR_DIS_CTRL[29..28]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_TFR_DIS_CTRL_SHFT        28
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_TFR_DIS_CTRL_ADDR        BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_TFR_DIS_CTRL_MASK        0x0C000000                // BSSID01_TFR_DIS_CTRL[27..26]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_TFR_DIS_CTRL_SHFT        26
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_TFR_DIS_CTRL_ADDR        BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_TFR_DIS_CTRL_MASK        0x03000000                // BSSID00_TFR_DIS_CTRL[25..24]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_TFR_DIS_CTRL_SHFT        24
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_ACTRL_PAD_SEL_ADDR       BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_ACTRL_PAD_SEL_MASK       0x00800000                // BSSID03_ACTRL_PAD_SEL[23]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID03_ACTRL_PAD_SEL_SHFT       23
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_ACTRL_PAD_SEL_ADDR       BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_ACTRL_PAD_SEL_MASK       0x00400000                // BSSID02_ACTRL_PAD_SEL[22]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID02_ACTRL_PAD_SEL_SHFT       22
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_ACTRL_PAD_SEL_ADDR       BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_ACTRL_PAD_SEL_MASK       0x00200000                // BSSID01_ACTRL_PAD_SEL[21]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID01_ACTRL_PAD_SEL_SHFT       21
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_ACTRL_PAD_SEL_ADDR       BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_ACTRL_PAD_SEL_MASK       0x00100000                // BSSID00_ACTRL_PAD_SEL[20]
#define BN0_WF_TMAC_TOP_TFCR2_BSSID00_ACTRL_PAD_SEL_SHFT       20
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_3_ADDR              BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_3_MASK              0x0000C000                // TRIG_GI_TYPE_3[15..14]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_3_SHFT              14
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_2_ADDR              BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_2_MASK              0x00003000                // TRIG_GI_TYPE_2[13..12]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_2_SHFT              12
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_1_ADDR              BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_1_MASK              0x00000C00                // TRIG_GI_TYPE_1[11..10]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_1_SHFT              10
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_0_ADDR              BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_0_MASK              0x00000300                // TRIG_GI_TYPE_0[9..8]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_GI_TYPE_0_SHFT              8
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_3_ADDR           BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_3_MASK           0x000000C0                // TRIG_HELTF_TYPE_3[7..6]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_3_SHFT           6
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_2_ADDR           BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_2_MASK           0x00000030                // TRIG_HELTF_TYPE_2[5..4]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_2_SHFT           4
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_1_ADDR           BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_1_MASK           0x0000000C                // TRIG_HELTF_TYPE_1[3..2]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_1_SHFT           2
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_0_ADDR           BN0_WF_TMAC_TOP_TFCR2_ADDR
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_0_MASK           0x00000003                // TRIG_HELTF_TYPE_0[1..0]
#define BN0_WF_TMAC_TOP_TFCR2_TRIG_HELTF_TYPE_0_SHFT           0

/* =====================================================================================

  ---TFCR3 (0x820E4000 + 0x1EC)---

    BSSID0_BSR_AC0_TID[2..0]     - (RW) BSR AC0 to TID mapping table for BSSID0
    RESERVED3[3]                 - (RO) Reserved bits
    BSSID0_BSR_AC1_TID[6..4]     - (RW) BSR AC1 to TID mapping table for BSSID0
    RESERVED7[7]                 - (RO) Reserved bits
    BSSID0_BSR_AC2_TID[10..8]    - (RW) BSR AC2 to TID mapping table for BSSID0
    RESERVED11[11]               - (RO) Reserved bits
    BSSID0_BSR_AC3_TID[14..12]   - (RW) BSR AC3 to TID mapping table for BSSID0
    RESERVED15[15]               - (RO) Reserved bits
    BSSID1_BSR_AC0_TID[18..16]   - (RW) BSR AC0 to TID mapping table for BSSID1
    RESERVED19[19]               - (RO) Reserved bits
    BSSID1_BSR_AC1_TID[22..20]   - (RW) BSR AC1 to TID mapping table for BSSID1
    RESERVED23[23]               - (RO) Reserved bits
    BSSID1_BSR_AC2_TID[26..24]   - (RW) BSR AC2 to TID mapping table for BSSID1
    RESERVED27[27]               - (RO) Reserved bits
    BSSID1_BSR_AC3_TID[30..28]   - (RW) BSR AC3 to TID mapping table for BSSID1
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC3_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC3_TID_MASK          0x70000000                // BSSID1_BSR_AC3_TID[30..28]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC3_TID_SHFT          28
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC2_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC2_TID_MASK          0x07000000                // BSSID1_BSR_AC2_TID[26..24]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC2_TID_SHFT          24
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC1_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC1_TID_MASK          0x00700000                // BSSID1_BSR_AC1_TID[22..20]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC1_TID_SHFT          20
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC0_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC0_TID_MASK          0x00070000                // BSSID1_BSR_AC0_TID[18..16]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID1_BSR_AC0_TID_SHFT          16
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC3_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC3_TID_MASK          0x00007000                // BSSID0_BSR_AC3_TID[14..12]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC3_TID_SHFT          12
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC2_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC2_TID_MASK          0x00000700                // BSSID0_BSR_AC2_TID[10..8]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC2_TID_SHFT          8
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC1_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC1_TID_MASK          0x00000070                // BSSID0_BSR_AC1_TID[6..4]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC1_TID_SHFT          4
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC0_TID_ADDR          BN0_WF_TMAC_TOP_TFCR3_ADDR
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC0_TID_MASK          0x00000007                // BSSID0_BSR_AC0_TID[2..0]
#define BN0_WF_TMAC_TOP_TFCR3_BSSID0_BSR_AC0_TID_SHFT          0

/* =====================================================================================

  ---FPCR (0x820E4000 + 0x23C)---

    RESERVED0[15..0]             - (RO) Reserved bits
    FRAME_POWER_MIN_DBM[23..16]  - (RW) Minimum TX power dBm
    FRAME_POWER_MAX_DBM[31..24]  - (RW) Maximum TX power dBm
                                     If B0_MAX_PWR_CHK_EN=1, VHT BW40/80/160 max Tx power dBm are only limited by VHT_FP0CR

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MAX_DBM_ADDR          BN0_WF_TMAC_TOP_FPCR_ADDR
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MAX_DBM_MASK          0xFF000000                // FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MAX_DBM_SHFT          24
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MIN_DBM_ADDR          BN0_WF_TMAC_TOP_FPCR_ADDR
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MIN_DBM_MASK          0x00FF0000                // FRAME_POWER_MIN_DBM[23..16]
#define BN0_WF_TMAC_TOP_FPCR_FRAME_POWER_MIN_DBM_SHFT          16

/* =====================================================================================

  ---DUCR0 (0x820E4000 + 0x240)---

    DUR_CR1[7..0]                - (RW) Duration CR1, for RTS protect MPDU/AMPDU
    DUR_CR2[15..8]               - (RW) Duration CR2, for next MPDU/AMPDU protection, if prior RX is non-HETB response
    DUR_CR7[23..16]              - (RW) Duration CR7, for next MPDU/AMPDU protection, if prior RX is HE_TB response
    RESERVED24[28..24]           - (RO) Reserved bits
    OPT_DUR_TRIG_RESP[29]        - (RW) select HE-TB response duration scheme
                                     0: TRIG duration = SIFS + HE_TB + DUR_CR3
                                     1: TRIG duration = SIFS + DUR_CR3
    OPT_DUR_RTS_TRIG[30]         - (RW) select RTS duration scheme
                                     0: RTS duration = SIFS + CTS + DUR_CR4
                                     1: RTS duration = SIFSx3 + CTS + TRIG + HE_TB + DUR_CR3
    OPT_DUR_RTS_DATA[31]         - (RW) select RTS duration scheme
                                     0: RTS duration = SIFS + CTS + DUR_CR1
                                     1: RTS duration = SIFSx2 + CTS + PPDU + (SIFS + HTP_ACK) / DUR_CR6

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_DATA_ADDR            BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_DATA_MASK            0x80000000                // OPT_DUR_RTS_DATA[31]
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_DATA_SHFT            31
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_TRIG_ADDR            BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_TRIG_MASK            0x40000000                // OPT_DUR_RTS_TRIG[30]
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_RTS_TRIG_SHFT            30
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_TRIG_RESP_ADDR           BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_TRIG_RESP_MASK           0x20000000                // OPT_DUR_TRIG_RESP[29]
#define BN0_WF_TMAC_TOP_DUCR0_OPT_DUR_TRIG_RESP_SHFT           29
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR7_ADDR                     BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR7_MASK                     0x00FF0000                // DUR_CR7[23..16]
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR7_SHFT                     16
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR2_ADDR                     BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR2_MASK                     0x0000FF00                // DUR_CR2[15..8]
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR2_SHFT                     8
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR1_ADDR                     BN0_WF_TMAC_TOP_DUCR0_ADDR
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR1_MASK                     0x000000FF                // DUR_CR1[7..0]
#define BN0_WF_TMAC_TOP_DUCR0_DUR_CR1_SHFT                     0

/* =====================================================================================

  ---DUCR1 (0x820E4000 + 0x244)---

    DUR_CR3[7..0]                - (RW) Duration CR3, for Trigger frame duration
    DUR_CR4[15..8]               - (RW) Duration CR4, for RTS protect trigger frame
    DUR_CR5[23..16]              - (RW) Duration CR5, trigger protect next ppdu
    DUR_CR6[31..24]              - (RW) Duration CR6, response time

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR6_ADDR                     BN0_WF_TMAC_TOP_DUCR1_ADDR
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR6_MASK                     0xFF000000                // DUR_CR6[31..24]
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR6_SHFT                     24
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR5_ADDR                     BN0_WF_TMAC_TOP_DUCR1_ADDR
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR5_MASK                     0x00FF0000                // DUR_CR5[23..16]
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR5_SHFT                     16
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR4_ADDR                     BN0_WF_TMAC_TOP_DUCR1_ADDR
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR4_MASK                     0x0000FF00                // DUR_CR4[15..8]
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR4_SHFT                     8
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR3_ADDR                     BN0_WF_TMAC_TOP_DUCR1_ADDR
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR3_MASK                     0x000000FF                // DUR_CR3[7..0]
#define BN0_WF_TMAC_TOP_DUCR1_DUR_CR3_SHFT                     0

/* =====================================================================================

  ---BRVHTCR0 (0x820E4000 + 0x250)---

    BFEE_VHT_RATE[12..0]         - (RW) TX rate for beamform report frame
                                     Bit[12:10]: Nsts: Count of space time stream
                                     3'b000: Nsts = 1
                                     3'b001: Nsts = 2
                                     3'b010: Nsts = 3
                                     3'b011: Nsts = 4
                                     3'b100: Nsts = 5
                                     3'b101: Nsts = 6
                                     3'b110: Nsts = 7
                                     3'b111: Nsts = 8
                                     Bit[9:6]: TX mode
                                     Indicates the transmission mode
                                     4'b0000: Legacy CCK
                                     4'b0001: Legacy OFDM
                                     4'b0010: HT mixed mode
                                     4'b0011: HT green field mode
                                     4'b0100: VHT mode
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     For HT rate:
                                     Bit 0~5 indicate MCSN, N=0~23 and 32, others reserved.
                                     For VHT rate:
                                     Bit 0~5 indicate MCSN, N=0~9, others reserved.
                                     For HE rate:
                                     Bit 0~4 indicate MCSN, N=)~``, other reserved
                                     Bit4 indicate HE DCM
                                     bit5 indicate HE_ER_SU 106Tone
    BFEE_VHT_STBC_EN[13]         - (RW) Enables STBC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/VHT only)
    BFEE_VHT_LDPC_EN[14]         - (RW) Enables LDPC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/VHT only)
    BFEE_VHT_DOPPLER[15]         - (RW) Doppler Enable
                                     1'b0: Disable
                                     1'b1: Enable (HE only)
    BFEE_VHT_PE[17..16]          - (RW) Max. PE for BF Report frame
                                     00: 0us
                                     01:8us
                                     10: 16us
                                     11: reserved
    RESERVED18[23..18]           - (RO) Reserved bits
    BFEE_VHT_GI_TYPE[25..24]     - (RW) GI Type
                                     HT/VHT
                                     2'b0: Normal GI
                                     2'b1: Short GI
                                     others: reserved
                                     HE:
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI
                                     others: reserved
    BFEE_VHT_HELTF_TYPE[27..26]  - (RW) indicate HE_LTF_TYPE
                                     2'h0: x1 LTF (3.2us)
                                     2'h1: x2 LTF (6.4us)
                                     2'h2: x4 LTF (12.8us)
                                     others: reserved
    BFEE_VHT_FIX_BW[29..28]      - (RW) TX bandwidth for beamform report frame
                                     2'b00: 20M BW
                                     2'b01: 40M BW
                                     2'b10: 80M BW
                                     2'b11: 160M BW/80+80M BW
    RESERVED30[30]               - (RO) Reserved bits
    BFEE_VHT_BW_SEL[31]          - (RW) Selects BW
                                     1'b0: Same as NDPA/NDP BW
                                     1'b1: Use fixed BW

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_BW_SEL_ADDR          BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_BW_SEL_MASK          0x80000000                // BFEE_VHT_BW_SEL[31]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_BW_SEL_SHFT          31
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_FIX_BW_ADDR          BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_FIX_BW_MASK          0x30000000                // BFEE_VHT_FIX_BW[29..28]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_FIX_BW_SHFT          28
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_HELTF_TYPE_ADDR      BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_HELTF_TYPE_MASK      0x0C000000                // BFEE_VHT_HELTF_TYPE[27..26]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_HELTF_TYPE_SHFT      26
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_GI_TYPE_ADDR         BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_GI_TYPE_MASK         0x03000000                // BFEE_VHT_GI_TYPE[25..24]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_GI_TYPE_SHFT         24
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_PE_ADDR              BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_PE_MASK              0x00030000                // BFEE_VHT_PE[17..16]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_PE_SHFT              16
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_DOPPLER_ADDR         BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_DOPPLER_MASK         0x00008000                // BFEE_VHT_DOPPLER[15]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_DOPPLER_SHFT         15
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_LDPC_EN_ADDR         BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_LDPC_EN_MASK         0x00004000                // BFEE_VHT_LDPC_EN[14]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_LDPC_EN_SHFT         14
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_STBC_EN_ADDR         BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_STBC_EN_MASK         0x00002000                // BFEE_VHT_STBC_EN[13]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_STBC_EN_SHFT         13
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_RATE_ADDR            BN0_WF_TMAC_TOP_BRVHTCR0_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_RATE_MASK            0x00001FFF                // BFEE_VHT_RATE[12..0]
#define BN0_WF_TMAC_TOP_BRVHTCR0_BFEE_VHT_RATE_SHFT            0

/* =====================================================================================

  ---BRVHTCR1 (0x820E4000 + 0x258)---

    BFEE_VHT_ANT_ID[11..0]       - (RW) Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BFEE_VHT_SPE_IDX[28..24]     - (RW) Spatial expansion table index for beamform report frame
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_SPE_IDX_ADDR         BN0_WF_TMAC_TOP_BRVHTCR1_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_SPE_IDX_MASK         0x1F000000                // BFEE_VHT_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_SPE_IDX_SHFT         24
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_ANT_ID_ADDR          BN0_WF_TMAC_TOP_BRVHTCR1_ADDR
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_ANT_ID_MASK          0x00000FFF                // BFEE_VHT_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_BRVHTCR1_BFEE_VHT_ANT_ID_SHFT          0

/* =====================================================================================

  ---BRHECR0 (0x820E4000 + 0x260)---

    BFEE_HE_RATE[12..0]          - (RW) TX rate for beamform report frame
                                     Bit[12:10]: Nsts: Count of space time stream
                                     3'b000: Nsts = 1
                                     3'b001: Nsts = 2
                                     3'b010: Nsts = 3
                                     3'b011: Nsts = 4
                                     3'b100: Nsts = 5
                                     3'b101: Nsts = 6
                                     3'b110: Nsts = 7
                                     3'b111: Nsts = 8
                                     Bit[9:6]: TX mode
                                     Indicates the transmission mode
                                     4'b0000: Legacy CCK
                                     4'b0001: Legacy OFDM
                                     4'b0010: HT mixed mode
                                     4'b0011: HT green field mode
                                     4'b0100: HE mode
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     For HT rate:
                                     Bit 0~5 indicate MCSN, N=0~23 and 32, others reserved.
                                     For HE rate:
                                     Bit 0~5 indicate MCSN, N=0~9, others reserved.
                                     For HE rate:
                                     Bit 0~4 indicate MCSN, N=)~``, other reserved
                                     Bit4 indicate HE DCM
                                     bit5 indicate HE_ER_SU 106Tone
    BFEE_HE_STBC_EN[13]          - (RW) Enables STBC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/HE only)
    BFEE_HE_LDPC_EN[14]          - (RW) Enables LDPC for beamform report frame
                                     1'b0: Disable
                                     1'b1: Enable (HT/HE only)
    BFEE_HE_DOPPLER[15]          - (RW) Doppler Enable
                                     1'b0: Disable
                                     1'b1: Enable (HE only)
    BFEE_HE_PE[17..16]           - (RW) Max. PE for BF Report frame
                                     00: 0us
                                     01:8us
                                     10: 16us
                                     11: reserved
    RESERVED18[23..18]           - (RO) Reserved bits
    BFEE_HE_GI_TYPE[25..24]      - (RW) GI Type
                                     HT/HE
                                     2'b0: Normal GI
                                     2'b1: Short GI
                                     others: reserved
                                     HE:
                                     2'h0: 0.8us GI
                                     2'h1: 1.6us GI
                                     2'h2: 3.2us GI
                                     others: reserved
    BFEE_HE_HELTF_TYPE[27..26]   - (RW) indicate HE_LTF_TYPE
                                     2'h0: x1 LTF (3.2us)
                                     2'h1: x2 LTF (6.4us)
                                     2'h2: x4 LTF (12.8us)
                                     others: reserved
    BFEE_HE_FIX_BW[29..28]       - (RW) TX bandwidth for beamform report frame
                                     2'b00: 20M BW
                                     2'b01: 40M BW
                                     2'b10: 80M BW
                                     2'b11: 160M BW/80+80M BW
    RESERVED30[30]               - (RO) Reserved bits
    BFEE_HE_BW_SEL[31]           - (RW) Selects BW
                                     1'b0: Same as NDPA/NDP BW
                                     1'b1: Use fixed BW

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_BW_SEL_ADDR            BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_BW_SEL_MASK            0x80000000                // BFEE_HE_BW_SEL[31]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_BW_SEL_SHFT            31
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_FIX_BW_ADDR            BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_FIX_BW_MASK            0x30000000                // BFEE_HE_FIX_BW[29..28]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_FIX_BW_SHFT            28
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_HELTF_TYPE_ADDR        BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_HELTF_TYPE_MASK        0x0C000000                // BFEE_HE_HELTF_TYPE[27..26]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_HELTF_TYPE_SHFT        26
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_GI_TYPE_ADDR           BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_GI_TYPE_MASK           0x03000000                // BFEE_HE_GI_TYPE[25..24]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_GI_TYPE_SHFT           24
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_PE_ADDR                BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_PE_MASK                0x00030000                // BFEE_HE_PE[17..16]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_PE_SHFT                16
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_DOPPLER_ADDR           BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_DOPPLER_MASK           0x00008000                // BFEE_HE_DOPPLER[15]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_DOPPLER_SHFT           15
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_LDPC_EN_ADDR           BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_LDPC_EN_MASK           0x00004000                // BFEE_HE_LDPC_EN[14]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_LDPC_EN_SHFT           14
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_STBC_EN_ADDR           BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_STBC_EN_MASK           0x00002000                // BFEE_HE_STBC_EN[13]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_STBC_EN_SHFT           13
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_RATE_ADDR              BN0_WF_TMAC_TOP_BRHECR0_ADDR
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_RATE_MASK              0x00001FFF                // BFEE_HE_RATE[12..0]
#define BN0_WF_TMAC_TOP_BRHECR0_BFEE_HE_RATE_SHFT              0

/* =====================================================================================

  ---BRHECR1 (0x820E4000 + 0x268)---

    BFEE_HE_ANT_ID[11..0]        - (RW) Smart antenna index
                                     bit[2:0]: Antenna 0
                                     bit[5:3]: Antenna 1
                                     bit[8:6]: Antenna 2
                                     bit[11:9]: Antenna 3
    RESERVED12[23..12]           - (RO) Reserved bits
    BFEE_HE_SPE_IDX[28..24]      - (RW) Spatial expansion table index for beamform report frame
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_SPE_IDX_ADDR           BN0_WF_TMAC_TOP_BRHECR1_ADDR
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_SPE_IDX_MASK           0x1F000000                // BFEE_HE_SPE_IDX[28..24]
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_SPE_IDX_SHFT           24
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_ANT_ID_ADDR            BN0_WF_TMAC_TOP_BRHECR1_ADDR
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_ANT_ID_MASK            0x00000FFF                // BFEE_HE_ANT_ID[11..0]
#define BN0_WF_TMAC_TOP_BRHECR1_BFEE_HE_ANT_ID_SHFT            0

/* =====================================================================================

  ---FP0R18 (0x820E4000 + 0x270)---

    HE26_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE26_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE26_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE26_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R18_HE26_3_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R18_ADDR
#define BN0_WF_TMAC_TOP_FP0R18_HE26_3_FRAME_POWER_DBM_MASK     0xFF000000                // HE26_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R18_HE26_3_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R18_HE26_2_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R18_ADDR
#define BN0_WF_TMAC_TOP_FP0R18_HE26_2_FRAME_POWER_DBM_MASK     0x00FF0000                // HE26_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R18_HE26_2_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R18_HE26_1_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R18_ADDR
#define BN0_WF_TMAC_TOP_FP0R18_HE26_1_FRAME_POWER_DBM_MASK     0x0000FF00                // HE26_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R18_HE26_1_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R18_HE26_0_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R18_ADDR
#define BN0_WF_TMAC_TOP_FP0R18_HE26_0_FRAME_POWER_DBM_MASK     0x000000FF                // HE26_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R18_HE26_0_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R19 (0x820E4000 + 0x274)---

    HE26_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE26_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE26_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE26_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R19_HE26_7_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R19_ADDR
#define BN0_WF_TMAC_TOP_FP0R19_HE26_7_FRAME_POWER_DBM_MASK     0xFF000000                // HE26_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R19_HE26_7_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R19_HE26_6_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R19_ADDR
#define BN0_WF_TMAC_TOP_FP0R19_HE26_6_FRAME_POWER_DBM_MASK     0x00FF0000                // HE26_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R19_HE26_6_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R19_HE26_5_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R19_ADDR
#define BN0_WF_TMAC_TOP_FP0R19_HE26_5_FRAME_POWER_DBM_MASK     0x0000FF00                // HE26_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R19_HE26_5_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R19_HE26_4_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R19_ADDR
#define BN0_WF_TMAC_TOP_FP0R19_HE26_4_FRAME_POWER_DBM_MASK     0x000000FF                // HE26_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R19_HE26_4_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R20 (0x820E4000 + 0x278)---

    HE26_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE26_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE26_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE26_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R20_HE26_11_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R20_ADDR
#define BN0_WF_TMAC_TOP_FP0R20_HE26_11_FRAME_POWER_DBM_MASK    0xFF000000                // HE26_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R20_HE26_11_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R20_HE26_10_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R20_ADDR
#define BN0_WF_TMAC_TOP_FP0R20_HE26_10_FRAME_POWER_DBM_MASK    0x00FF0000                // HE26_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R20_HE26_10_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R20_HE26_9_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R20_ADDR
#define BN0_WF_TMAC_TOP_FP0R20_HE26_9_FRAME_POWER_DBM_MASK     0x0000FF00                // HE26_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R20_HE26_9_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R20_HE26_8_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R20_ADDR
#define BN0_WF_TMAC_TOP_FP0R20_HE26_8_FRAME_POWER_DBM_MASK     0x000000FF                // HE26_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R20_HE26_8_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R21 (0x820E4000 + 0x27C)---

    HE52_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE52_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE52_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE52_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R21_HE52_3_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R21_ADDR
#define BN0_WF_TMAC_TOP_FP0R21_HE52_3_FRAME_POWER_DBM_MASK     0xFF000000                // HE52_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R21_HE52_3_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R21_HE52_2_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R21_ADDR
#define BN0_WF_TMAC_TOP_FP0R21_HE52_2_FRAME_POWER_DBM_MASK     0x00FF0000                // HE52_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R21_HE52_2_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R21_HE52_1_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R21_ADDR
#define BN0_WF_TMAC_TOP_FP0R21_HE52_1_FRAME_POWER_DBM_MASK     0x0000FF00                // HE52_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R21_HE52_1_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R21_HE52_0_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R21_ADDR
#define BN0_WF_TMAC_TOP_FP0R21_HE52_0_FRAME_POWER_DBM_MASK     0x000000FF                // HE52_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R21_HE52_0_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R22 (0x820E4000 + 0x280)---

    HE52_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE52_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE52_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE52_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R22_HE52_7_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R22_ADDR
#define BN0_WF_TMAC_TOP_FP0R22_HE52_7_FRAME_POWER_DBM_MASK     0xFF000000                // HE52_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R22_HE52_7_FRAME_POWER_DBM_SHFT     24
#define BN0_WF_TMAC_TOP_FP0R22_HE52_6_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R22_ADDR
#define BN0_WF_TMAC_TOP_FP0R22_HE52_6_FRAME_POWER_DBM_MASK     0x00FF0000                // HE52_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R22_HE52_6_FRAME_POWER_DBM_SHFT     16
#define BN0_WF_TMAC_TOP_FP0R22_HE52_5_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R22_ADDR
#define BN0_WF_TMAC_TOP_FP0R22_HE52_5_FRAME_POWER_DBM_MASK     0x0000FF00                // HE52_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R22_HE52_5_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R22_HE52_4_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R22_ADDR
#define BN0_WF_TMAC_TOP_FP0R22_HE52_4_FRAME_POWER_DBM_MASK     0x000000FF                // HE52_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R22_HE52_4_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R23 (0x820E4000 + 0x284)---

    HE52_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE52_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE52_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE52_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R23_HE52_11_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R23_ADDR
#define BN0_WF_TMAC_TOP_FP0R23_HE52_11_FRAME_POWER_DBM_MASK    0xFF000000                // HE52_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R23_HE52_11_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R23_HE52_10_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R23_ADDR
#define BN0_WF_TMAC_TOP_FP0R23_HE52_10_FRAME_POWER_DBM_MASK    0x00FF0000                // HE52_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R23_HE52_10_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R23_HE52_9_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R23_ADDR
#define BN0_WF_TMAC_TOP_FP0R23_HE52_9_FRAME_POWER_DBM_MASK     0x0000FF00                // HE52_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R23_HE52_9_FRAME_POWER_DBM_SHFT     8
#define BN0_WF_TMAC_TOP_FP0R23_HE52_8_FRAME_POWER_DBM_ADDR     BN0_WF_TMAC_TOP_FP0R23_ADDR
#define BN0_WF_TMAC_TOP_FP0R23_HE52_8_FRAME_POWER_DBM_MASK     0x000000FF                // HE52_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R23_HE52_8_FRAME_POWER_DBM_SHFT     0

/* =====================================================================================

  ---FP0R24 (0x820E4000 + 0x288)---

    HE106_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE106_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE106_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE106_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R24_HE106_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R24_ADDR
#define BN0_WF_TMAC_TOP_FP0R24_HE106_3_FRAME_POWER_DBM_MASK    0xFF000000                // HE106_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R24_HE106_3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R24_HE106_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R24_ADDR
#define BN0_WF_TMAC_TOP_FP0R24_HE106_2_FRAME_POWER_DBM_MASK    0x00FF0000                // HE106_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R24_HE106_2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R24_HE106_1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R24_ADDR
#define BN0_WF_TMAC_TOP_FP0R24_HE106_1_FRAME_POWER_DBM_MASK    0x0000FF00                // HE106_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R24_HE106_1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R24_HE106_0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R24_ADDR
#define BN0_WF_TMAC_TOP_FP0R24_HE106_0_FRAME_POWER_DBM_MASK    0x000000FF                // HE106_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R24_HE106_0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R25 (0x820E4000 + 0x28C)---

    HE106_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE106_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE106_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE106_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R25_HE106_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R25_ADDR
#define BN0_WF_TMAC_TOP_FP0R25_HE106_7_FRAME_POWER_DBM_MASK    0xFF000000                // HE106_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R25_HE106_7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R25_HE106_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R25_ADDR
#define BN0_WF_TMAC_TOP_FP0R25_HE106_6_FRAME_POWER_DBM_MASK    0x00FF0000                // HE106_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R25_HE106_6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R25_HE106_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R25_ADDR
#define BN0_WF_TMAC_TOP_FP0R25_HE106_5_FRAME_POWER_DBM_MASK    0x0000FF00                // HE106_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R25_HE106_5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R25_HE106_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R25_ADDR
#define BN0_WF_TMAC_TOP_FP0R25_HE106_4_FRAME_POWER_DBM_MASK    0x000000FF                // HE106_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R25_HE106_4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R26 (0x820E4000 + 0x290)---

    HE106_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE106_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE106_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE106_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R26_HE106_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R26_ADDR
#define BN0_WF_TMAC_TOP_FP0R26_HE106_11_FRAME_POWER_DBM_MASK   0xFF000000                // HE106_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R26_HE106_11_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R26_HE106_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R26_ADDR
#define BN0_WF_TMAC_TOP_FP0R26_HE106_10_FRAME_POWER_DBM_MASK   0x00FF0000                // HE106_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R26_HE106_10_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R26_HE106_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R26_ADDR
#define BN0_WF_TMAC_TOP_FP0R26_HE106_9_FRAME_POWER_DBM_MASK    0x0000FF00                // HE106_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R26_HE106_9_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R26_HE106_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R26_ADDR
#define BN0_WF_TMAC_TOP_FP0R26_HE106_8_FRAME_POWER_DBM_MASK    0x000000FF                // HE106_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R26_HE106_8_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R27 (0x820E4000 + 0x294)---

    HE242_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE242_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE242_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE242_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R27_HE242_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R27_ADDR
#define BN0_WF_TMAC_TOP_FP0R27_HE242_3_FRAME_POWER_DBM_MASK    0xFF000000                // HE242_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R27_HE242_3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R27_HE242_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R27_ADDR
#define BN0_WF_TMAC_TOP_FP0R27_HE242_2_FRAME_POWER_DBM_MASK    0x00FF0000                // HE242_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R27_HE242_2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R27_HE242_1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R27_ADDR
#define BN0_WF_TMAC_TOP_FP0R27_HE242_1_FRAME_POWER_DBM_MASK    0x0000FF00                // HE242_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R27_HE242_1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R27_HE242_0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R27_ADDR
#define BN0_WF_TMAC_TOP_FP0R27_HE242_0_FRAME_POWER_DBM_MASK    0x000000FF                // HE242_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R27_HE242_0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R28 (0x820E4000 + 0x298)---

    HE242_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE242_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE242_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE242_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R28_HE242_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R28_ADDR
#define BN0_WF_TMAC_TOP_FP0R28_HE242_7_FRAME_POWER_DBM_MASK    0xFF000000                // HE242_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R28_HE242_7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R28_HE242_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R28_ADDR
#define BN0_WF_TMAC_TOP_FP0R28_HE242_6_FRAME_POWER_DBM_MASK    0x00FF0000                // HE242_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R28_HE242_6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R28_HE242_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R28_ADDR
#define BN0_WF_TMAC_TOP_FP0R28_HE242_5_FRAME_POWER_DBM_MASK    0x0000FF00                // HE242_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R28_HE242_5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R28_HE242_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R28_ADDR
#define BN0_WF_TMAC_TOP_FP0R28_HE242_4_FRAME_POWER_DBM_MASK    0x000000FF                // HE242_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R28_HE242_4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R29 (0x820E4000 + 0x29C)---

    HE242_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE242_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE242_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE242_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R29_HE242_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R29_ADDR
#define BN0_WF_TMAC_TOP_FP0R29_HE242_11_FRAME_POWER_DBM_MASK   0xFF000000                // HE242_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R29_HE242_11_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R29_HE242_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R29_ADDR
#define BN0_WF_TMAC_TOP_FP0R29_HE242_10_FRAME_POWER_DBM_MASK   0x00FF0000                // HE242_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R29_HE242_10_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R29_HE242_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R29_ADDR
#define BN0_WF_TMAC_TOP_FP0R29_HE242_9_FRAME_POWER_DBM_MASK    0x0000FF00                // HE242_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R29_HE242_9_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R29_HE242_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R29_ADDR
#define BN0_WF_TMAC_TOP_FP0R29_HE242_8_FRAME_POWER_DBM_MASK    0x000000FF                // HE242_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R29_HE242_8_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R30 (0x820E4000 + 0x2A0)---

    HE484_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE484_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE484_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE484_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R30_HE484_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R30_ADDR
#define BN0_WF_TMAC_TOP_FP0R30_HE484_3_FRAME_POWER_DBM_MASK    0xFF000000                // HE484_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R30_HE484_3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R30_HE484_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R30_ADDR
#define BN0_WF_TMAC_TOP_FP0R30_HE484_2_FRAME_POWER_DBM_MASK    0x00FF0000                // HE484_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R30_HE484_2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R30_HE484_1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R30_ADDR
#define BN0_WF_TMAC_TOP_FP0R30_HE484_1_FRAME_POWER_DBM_MASK    0x0000FF00                // HE484_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R30_HE484_1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R30_HE484_0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R30_ADDR
#define BN0_WF_TMAC_TOP_FP0R30_HE484_0_FRAME_POWER_DBM_MASK    0x000000FF                // HE484_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R30_HE484_0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R31 (0x820E4000 + 0x2A4)---

    HE484_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE484_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE484_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE484_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R31_HE484_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R31_ADDR
#define BN0_WF_TMAC_TOP_FP0R31_HE484_7_FRAME_POWER_DBM_MASK    0xFF000000                // HE484_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R31_HE484_7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R31_HE484_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R31_ADDR
#define BN0_WF_TMAC_TOP_FP0R31_HE484_6_FRAME_POWER_DBM_MASK    0x00FF0000                // HE484_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R31_HE484_6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R31_HE484_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R31_ADDR
#define BN0_WF_TMAC_TOP_FP0R31_HE484_5_FRAME_POWER_DBM_MASK    0x0000FF00                // HE484_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R31_HE484_5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R31_HE484_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R31_ADDR
#define BN0_WF_TMAC_TOP_FP0R31_HE484_4_FRAME_POWER_DBM_MASK    0x000000FF                // HE484_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R31_HE484_4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R32 (0x820E4000 + 0x2A8)---

    HE484_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE484_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE484_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE484_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R32_HE484_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R32_ADDR
#define BN0_WF_TMAC_TOP_FP0R32_HE484_11_FRAME_POWER_DBM_MASK   0xFF000000                // HE484_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R32_HE484_11_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R32_HE484_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R32_ADDR
#define BN0_WF_TMAC_TOP_FP0R32_HE484_10_FRAME_POWER_DBM_MASK   0x00FF0000                // HE484_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R32_HE484_10_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R32_HE484_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R32_ADDR
#define BN0_WF_TMAC_TOP_FP0R32_HE484_9_FRAME_POWER_DBM_MASK    0x0000FF00                // HE484_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R32_HE484_9_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R32_HE484_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R32_ADDR
#define BN0_WF_TMAC_TOP_FP0R32_HE484_8_FRAME_POWER_DBM_MASK    0x000000FF                // HE484_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R32_HE484_8_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R33 (0x820E4000 + 0x2AC)---

    HE996_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE996_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE996_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE996_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R33_HE996_3_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R33_ADDR
#define BN0_WF_TMAC_TOP_FP0R33_HE996_3_FRAME_POWER_DBM_MASK    0xFF000000                // HE996_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R33_HE996_3_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R33_HE996_2_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R33_ADDR
#define BN0_WF_TMAC_TOP_FP0R33_HE996_2_FRAME_POWER_DBM_MASK    0x00FF0000                // HE996_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R33_HE996_2_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R33_HE996_1_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R33_ADDR
#define BN0_WF_TMAC_TOP_FP0R33_HE996_1_FRAME_POWER_DBM_MASK    0x0000FF00                // HE996_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R33_HE996_1_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R33_HE996_0_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R33_ADDR
#define BN0_WF_TMAC_TOP_FP0R33_HE996_0_FRAME_POWER_DBM_MASK    0x000000FF                // HE996_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R33_HE996_0_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R34 (0x820E4000 + 0x2B0)---

    HE996_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE996_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE996_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE996_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R34_HE996_7_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R34_ADDR
#define BN0_WF_TMAC_TOP_FP0R34_HE996_7_FRAME_POWER_DBM_MASK    0xFF000000                // HE996_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R34_HE996_7_FRAME_POWER_DBM_SHFT    24
#define BN0_WF_TMAC_TOP_FP0R34_HE996_6_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R34_ADDR
#define BN0_WF_TMAC_TOP_FP0R34_HE996_6_FRAME_POWER_DBM_MASK    0x00FF0000                // HE996_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R34_HE996_6_FRAME_POWER_DBM_SHFT    16
#define BN0_WF_TMAC_TOP_FP0R34_HE996_5_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R34_ADDR
#define BN0_WF_TMAC_TOP_FP0R34_HE996_5_FRAME_POWER_DBM_MASK    0x0000FF00                // HE996_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R34_HE996_5_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R34_HE996_4_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R34_ADDR
#define BN0_WF_TMAC_TOP_FP0R34_HE996_4_FRAME_POWER_DBM_MASK    0x000000FF                // HE996_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R34_HE996_4_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R35 (0x820E4000 + 0x2B4)---

    HE996_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE996_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE996_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE996_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R35_HE996_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R35_ADDR
#define BN0_WF_TMAC_TOP_FP0R35_HE996_11_FRAME_POWER_DBM_MASK   0xFF000000                // HE996_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R35_HE996_11_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R35_HE996_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R35_ADDR
#define BN0_WF_TMAC_TOP_FP0R35_HE996_10_FRAME_POWER_DBM_MASK   0x00FF0000                // HE996_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R35_HE996_10_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R35_HE996_9_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R35_ADDR
#define BN0_WF_TMAC_TOP_FP0R35_HE996_9_FRAME_POWER_DBM_MASK    0x0000FF00                // HE996_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R35_HE996_9_FRAME_POWER_DBM_SHFT    8
#define BN0_WF_TMAC_TOP_FP0R35_HE996_8_FRAME_POWER_DBM_ADDR    BN0_WF_TMAC_TOP_FP0R35_ADDR
#define BN0_WF_TMAC_TOP_FP0R35_HE996_8_FRAME_POWER_DBM_MASK    0x000000FF                // HE996_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R35_HE996_8_FRAME_POWER_DBM_SHFT    0

/* =====================================================================================

  ---FP0R36 (0x820E4000 + 0x2B8)---

    HE996X2_0_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For BPSK modulation. (MCS0)
    HE996X2_1_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS1)
    HE996X2_2_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For QPSK modulation. (MCS2)
    HE996X2_3_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS3)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_3_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R36_ADDR
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_3_FRAME_POWER_DBM_MASK  0xFF000000                // HE996X2_3_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_3_FRAME_POWER_DBM_SHFT  24
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_2_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R36_ADDR
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_2_FRAME_POWER_DBM_MASK  0x00FF0000                // HE996X2_2_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_2_FRAME_POWER_DBM_SHFT  16
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_1_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R36_ADDR
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_1_FRAME_POWER_DBM_MASK  0x0000FF00                // HE996X2_1_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_1_FRAME_POWER_DBM_SHFT  8
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_0_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R36_ADDR
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_0_FRAME_POWER_DBM_MASK  0x000000FF                // HE996X2_0_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R36_HE996X2_0_FRAME_POWER_DBM_SHFT  0

/* =====================================================================================

  ---FP0R37 (0x820E4000 + 0x2BC)---

    HE996X2_4_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 16-QAM modulation. (MCS4)
    HE996X2_5_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS5)
    HE996X2_6_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS6)
    HE996X2_7_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 64-QAM modulation. (MCS7)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_7_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R37_ADDR
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_7_FRAME_POWER_DBM_MASK  0xFF000000                // HE996X2_7_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_7_FRAME_POWER_DBM_SHFT  24
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_6_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R37_ADDR
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_6_FRAME_POWER_DBM_MASK  0x00FF0000                // HE996X2_6_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_6_FRAME_POWER_DBM_SHFT  16
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_5_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R37_ADDR
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_5_FRAME_POWER_DBM_MASK  0x0000FF00                // HE996X2_5_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_5_FRAME_POWER_DBM_SHFT  8
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_4_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R37_ADDR
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_4_FRAME_POWER_DBM_MASK  0x000000FF                // HE996X2_4_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R37_HE996X2_4_FRAME_POWER_DBM_SHFT  0

/* =====================================================================================

  ---FP0R38 (0x820E4000 + 0x2C0)---

    HE996X2_8_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS8)
    HE996X2_9_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 256-QAM modulation. (MCS9)
    HE996X2_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    HE996X2_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_11_FRAME_POWER_DBM_ADDR BN0_WF_TMAC_TOP_FP0R38_ADDR
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_11_FRAME_POWER_DBM_MASK 0xFF000000                // HE996X2_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_11_FRAME_POWER_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_10_FRAME_POWER_DBM_ADDR BN0_WF_TMAC_TOP_FP0R38_ADDR
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_10_FRAME_POWER_DBM_MASK 0x00FF0000                // HE996X2_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_10_FRAME_POWER_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_9_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R38_ADDR
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_9_FRAME_POWER_DBM_MASK  0x0000FF00                // HE996X2_9_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_9_FRAME_POWER_DBM_SHFT  8
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_8_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R38_ADDR
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_8_FRAME_POWER_DBM_MASK  0x000000FF                // HE996X2_8_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R38_HE996X2_8_FRAME_POWER_DBM_SHFT  0

/* =====================================================================================

  ---FP0R39 (0x820E4000 + 0x2C4)---

    VHT20_10_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    VHT20_11_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)
    VHT40_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    VHT40_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R39_ADDR
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_11_FRAME_POWER_DBM_MASK   0xFF000000                // VHT40_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_11_FRAME_POWER_DBM_SHFT   24
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R39_ADDR
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_10_FRAME_POWER_DBM_MASK   0x00FF0000                // VHT40_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R39_VHT40_10_FRAME_POWER_DBM_SHFT   16
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R39_ADDR
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_11_FRAME_POWER_DBM_MASK   0x0000FF00                // VHT20_11_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_11_FRAME_POWER_DBM_SHFT   8
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R39_ADDR
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_10_FRAME_POWER_DBM_MASK   0x000000FF                // VHT20_10_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R39_VHT20_10_FRAME_POWER_DBM_SHFT   0

/* =====================================================================================

  ---FP0R40 (0x820E4000 + 0x2C8)---

    VHT80_10_FRAME_POWER_DBM[7..0] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    VHT80_11_FRAME_POWER_DBM[15..8] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)
    VHT160_10_FRAME_POWER_DBM[23..16] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS10)
    VHT160_11_FRAME_POWER_DBM[31..24] - (RW) Same as LG_OFDM3_FRAME_POWER_DBM
                                     For 1024-QAM modulation. (MCS11)

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_11_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R40_ADDR
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_11_FRAME_POWER_DBM_MASK  0xFF000000                // VHT160_11_FRAME_POWER_DBM[31..24]
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_11_FRAME_POWER_DBM_SHFT  24
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_10_FRAME_POWER_DBM_ADDR  BN0_WF_TMAC_TOP_FP0R40_ADDR
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_10_FRAME_POWER_DBM_MASK  0x00FF0000                // VHT160_10_FRAME_POWER_DBM[23..16]
#define BN0_WF_TMAC_TOP_FP0R40_VHT160_10_FRAME_POWER_DBM_SHFT  16
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_11_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R40_ADDR
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_11_FRAME_POWER_DBM_MASK   0x0000FF00                // VHT80_11_FRAME_POWER_DBM[15..8]
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_11_FRAME_POWER_DBM_SHFT   8
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_10_FRAME_POWER_DBM_ADDR   BN0_WF_TMAC_TOP_FP0R40_ADDR
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_10_FRAME_POWER_DBM_MASK   0x000000FF                // VHT80_10_FRAME_POWER_DBM[7..0]
#define BN0_WF_TMAC_TOP_FP0R40_VHT80_10_FRAME_POWER_DBM_SHFT   0

/* =====================================================================================

  ---HE_FP0CR0 (0x820E4000 + 0x2D0)---

    HE242_FRAME_POWER_MAX_DBM[7..0] - (RW) HE BW 242 Maximum TX power dBm 
                                     HE242_FRAME_POWER_MAX_DBM is applied
    HE484_FRAME_POWER_MAX_DBM[15..8] - (RW) HE BW 484 Maximum TX power dBm 
                                     HE484_FRAME_POWER_MAX_DBM is applied
    HE996_FRAME_POWER_MAX_DBM[23..16] - (RW) HE BW 996 Maximum TX power dBm 
                                     HE996_FRAME_POWER_MAX_DBM is applied
    HE996X2_FRAME_POWER_MAX_DBM[31..24] - (RW) HE BW 996X2 Maximum TX power dBm 
                                     HE996X2_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996X2_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996X2_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // HE996X2_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996X2_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // HE996_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE996_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE484_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE484_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // HE484_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE484_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE242_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE242_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // HE242_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_HE_FP0CR0_HE242_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---HE_FP0CR1 (0x820E4000 + 0x2D4)---

    RESERVED0[7..0]              - (RO) Reserved bits
    HE26_FRAME_POWER_MAX_DBM[15..8] - (RW) HE BW 26 Maximum TX power dBm 
                                     HE26_FRAME_POWER_MAX_DBM is applied
    HE52_FRAME_POWER_MAX_DBM[23..16] - (RW) HE BW 52 Maximum TX power dBm 
                                     HE52_FRAME_POWER_MAX_DBM is applied
    HE106_FRAME_POWER_MAX_DBM[31..24] - (RW) HE BW 106 Maximum TX power dBm 
                                     HE106_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE106_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR1_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE106_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // HE106_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE106_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE52_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR1_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE52_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // HE52_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE52_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE26_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_HE_FP0CR1_ADDR
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE26_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // HE26_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_HE_FP0CR1_HE26_FRAME_POWER_MAX_DBM_SHFT 8

/* =====================================================================================

  ---SRU_FP0CR0 (0x820E4000 + 0x2D8)---

    RU26BW20_LO_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW20 Lower corner Maximum TX power dBm 
                                     RU26BW20_LO_FRAME_POWER_MAX_DBM is applied
    RU52BW20_LO_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW20 Lower corner Maximum TX power dBm 
                                     RU52BW20_LO_FRAME_POWER_MAX_DBM is applied
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU52BW20_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU52BW20_LO_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW20_LO_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU52BW20_LO_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU26BW20_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR0_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU26BW20_LO_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW20_LO_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR0_RU26BW20_LO_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR1 (0x820E4000 + 0x2DC)---

    RU26BW20_CE_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW20 Center corner Maximum TX power dBm 
                                     RU26BW20_CE_FRAME_POWER_MAX_DBM is applied
    RU52BW20_CE_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW20 Center corner Maximum TX power dBm 
                                     RU52BW20_CE_FRAME_POWER_MAX_DBM is applied
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU52BW20_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR1_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU52BW20_CE_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW20_CE_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU52BW20_CE_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU26BW20_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR1_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU26BW20_CE_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW20_CE_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR1_RU26BW20_CE_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR2 (0x820E4000 + 0x2E0)---

    RU26BW20_HI_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW20 Higher corner Maximum TX power dBm 
                                     RU26BW20_HI_FRAME_POWER_MAX_DBM is applied
    RU52BW20_HI_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW20 Higher corner Maximum TX power dBm 
                                     RU52BW20_HI_FRAME_POWER_MAX_DBM is applied
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU52BW20_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR2_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU52BW20_HI_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW20_HI_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU52BW20_HI_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU26BW20_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR2_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU26BW20_HI_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW20_HI_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR2_RU26BW20_HI_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR3 (0x820E4000 + 0x2E4)---

    RU26BW40_LO_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW40 Lower corner Maximum TX power dBm 
                                     RU26BW40_LO_FRAME_POWER_MAX_DBM is applied
    RU52BW40_LO_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW40 Lower corner Maximum TX power dBm 
                                     RU52BW40_LO_FRAME_POWER_MAX_DBM is applied
    RU106BW40_LO_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW40 Lower corner Maximum TX power dBm 
                                     RU106BW40_LO_FRAME_POWER_MAX_DBM is applied
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU106BW40_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR3_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU106BW40_LO_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW40_LO_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU106BW40_LO_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU52BW40_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR3_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU52BW40_LO_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW40_LO_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU52BW40_LO_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU26BW40_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR3_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU26BW40_LO_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW40_LO_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR3_RU26BW40_LO_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR4 (0x820E4000 + 0x2E8)---

    RU26BW40_CE_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW40 Center corner Maximum TX power dBm 
                                     RU26BW40_CE_FRAME_POWER_MAX_DBM is applied
    RU52BW40_CE_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW40 Center corner Maximum TX power dBm 
                                     RU52BW40_CE_FRAME_POWER_MAX_DBM is applied
    RU106BW40_CE_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW40 Center corner Maximum TX power dBm 
                                     RU106BW40_CE_FRAME_POWER_MAX_DBM is applied
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU106BW40_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR4_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU106BW40_CE_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW40_CE_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU106BW40_CE_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU52BW40_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR4_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU52BW40_CE_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW40_CE_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU52BW40_CE_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU26BW40_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR4_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU26BW40_CE_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW40_CE_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR4_RU26BW40_CE_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR5 (0x820E4000 + 0x2EC)---

    RU26BW40_HI_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW40 Higher corner Maximum TX power dBm 
                                     RU26BW40_HI_FRAME_POWER_MAX_DBM is applied
    RU52BW40_HI_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW40 Higher corner Maximum TX power dBm 
                                     RU52BW40_HI_FRAME_POWER_MAX_DBM is applied
    RU106BW40_HI_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW40 Higher corner Maximum TX power dBm 
                                     RU106BW40_HI_FRAME_POWER_MAX_DBM is applied
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU106BW40_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR5_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU106BW40_HI_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW40_HI_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU106BW40_HI_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU52BW40_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR5_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU52BW40_HI_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW40_HI_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU52BW40_HI_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU26BW40_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR5_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU26BW40_HI_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW40_HI_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR5_RU26BW40_HI_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR6 (0x820E4000 + 0x2F0)---

    RU26BW80_LO_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW80 Lower corner Maximum TX power dBm 
                                     RU26BW80_LO_FRAME_POWER_MAX_DBM is applied
    RU52BW80_LO_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW80 Lower corner Maximum TX power dBm 
                                     RU52BW80_LO_FRAME_POWER_MAX_DBM is applied
    RU106BW80_LO_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW80 Lower corner Maximum TX power dBm 
                                     RU106BW80_LO_FRAME_POWER_MAX_DBM is applied
    RU242BW80_LO_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW80 Lower corner Maximum TX power dBm 
                                     RU106BW80_LO_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU242BW80_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR6_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU242BW80_LO_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW80_LO_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU242BW80_LO_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU106BW80_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR6_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU106BW80_LO_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW80_LO_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU106BW80_LO_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU52BW80_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR6_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU52BW80_LO_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW80_LO_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU52BW80_LO_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU26BW80_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR6_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU26BW80_LO_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW80_LO_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR6_RU26BW80_LO_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR7 (0x820E4000 + 0x2F4)---

    RU26BW80_CE_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW80 Center corner Maximum TX power dBm 
                                     RU26BW80_CE_FRAME_POWER_MAX_DBM is applied
    RU52BW80_CE_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW80 Center corner Maximum TX power dBm 
                                     RU52BW80_CE_FRAME_POWER_MAX_DBM is applied
    RU106BW80_CE_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW80 Center corner Maximum TX power dBm 
                                     RU106BW80_CE_FRAME_POWER_MAX_DBM is applied
    RU242BW80_CE_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW80 Center corner Maximum TX power dBm 
                                     RU106BW80_CE_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU242BW80_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR7_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU242BW80_CE_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW80_CE_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU242BW80_CE_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU106BW80_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR7_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU106BW80_CE_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW80_CE_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU106BW80_CE_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU52BW80_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR7_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU52BW80_CE_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW80_CE_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU52BW80_CE_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU26BW80_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR7_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU26BW80_CE_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW80_CE_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR7_RU26BW80_CE_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR8 (0x820E4000 + 0x2F8)---

    RU26BW80_HI_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW80 Higher corner Maximum TX power dBm 
                                     RU26BW80_HI_FRAME_POWER_MAX_DBM is applied
    RU52BW80_HI_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW80 Higher corner Maximum TX power dBm 
                                     RU52BW80_HI_FRAME_POWER_MAX_DBM is applied
    RU106BW80_HI_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW80 Higher corner Maximum TX power dBm 
                                     RU106BW80_HI_FRAME_POWER_MAX_DBM is applied
    RU242BW80_HI_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW80 Higher corner Maximum TX power dBm 
                                     RU106BW80_HI_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU242BW80_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR8_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU242BW80_HI_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW80_HI_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU242BW80_HI_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU106BW80_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR8_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU106BW80_HI_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW80_HI_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU106BW80_HI_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU52BW80_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR8_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU52BW80_HI_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW80_HI_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU52BW80_HI_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU26BW80_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR8_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU26BW80_HI_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW80_HI_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR8_RU26BW80_HI_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR9 (0x820E4000 + 0x2FC)---

    RU26BW160_LO_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW160 Lower corner Maximum TX power dBm 
                                     RU26BW160_LO_FRAME_POWER_MAX_DBM is applied
    RU52BW160_LO_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW160 Lower corner Maximum TX power dBm 
                                     RU52BW160_LO_FRAME_POWER_MAX_DBM is applied
    RU106BW160_LO_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW160 Lower corner Maximum TX power dBm 
                                     RU106BW160_LO_FRAME_POWER_MAX_DBM is applied
    RU242BW160_LO_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW160 Lower corner Maximum TX power dBm 
                                     RU106BW160_LO_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU242BW160_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR9_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU242BW160_LO_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW160_LO_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU242BW160_LO_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU106BW160_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR9_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU106BW160_LO_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW160_LO_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU106BW160_LO_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU52BW160_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR9_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU52BW160_LO_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW160_LO_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU52BW160_LO_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU26BW160_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR9_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU26BW160_LO_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW160_LO_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR9_RU26BW160_LO_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR10 (0x820E4000 + 0x300)---

    RU26BW160_CE_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW160 Center corner Maximum TX power dBm 
                                     RU26BW160_CE_FRAME_POWER_MAX_DBM is applied
    RU52BW160_CE_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW160 Center corner Maximum TX power dBm 
                                     RU52BW160_CE_FRAME_POWER_MAX_DBM is applied
    RU106BW160_CE_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW160 Center corner Maximum TX power dBm 
                                     RU106BW160_CE_FRAME_POWER_MAX_DBM is applied
    RU242BW160_CE_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW160 Center corner Maximum TX power dBm 
                                     RU106BW160_CE_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU242BW160_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR10_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU242BW160_CE_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW160_CE_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU242BW160_CE_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU106BW160_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR10_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU106BW160_CE_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW160_CE_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU106BW160_CE_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU52BW160_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR10_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU52BW160_CE_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW160_CE_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU52BW160_CE_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU26BW160_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR10_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU26BW160_CE_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW160_CE_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR10_RU26BW160_CE_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR11 (0x820E4000 + 0x304)---

    RU26BW160_HI_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU26 in DBW160 Higher corner Maximum TX power dBm 
                                     RU26BW160_HI_FRAME_POWER_MAX_DBM is applied
    RU52BW160_HI_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU52 in DBW160 Higher corner Maximum TX power dBm 
                                     RU52BW160_HI_FRAME_POWER_MAX_DBM is applied
    RU106BW160_HI_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU106 in DBW160 Higher corner Maximum TX power dBm 
                                     RU106BW160_HI_FRAME_POWER_MAX_DBM is applied
    RU242BW160_HI_FRAME_POWER_MAX_DBM[31..24] - (RW) Small RU242 in DBW160 Higher corner Maximum TX power dBm 
                                     RU106BW160_HI_FRAME_POWER_MAX_DBM is applied

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU242BW160_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR11_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU242BW160_HI_FRAME_POWER_MAX_DBM_MASK 0xFF000000                // RU242BW160_HI_FRAME_POWER_MAX_DBM[31..24]
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU242BW160_HI_FRAME_POWER_MAX_DBM_SHFT 24
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU106BW160_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR11_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU106BW160_HI_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW160_HI_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU106BW160_HI_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU52BW160_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR11_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU52BW160_HI_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU52BW160_HI_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU52BW160_HI_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU26BW160_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR11_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU26BW160_HI_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU26BW160_HI_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR11_RU26BW160_HI_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---SRU_FP0CR12 (0x820E4000 + 0x308)---

    RU106BW160_LO_FRAME_POWER_MAX_DBM[7..0] - (RW) Small RU484 in DBW160 Lower corner Maximum TX power dBm 
                                     RU106BW160_HI_FRAME_POWER_MAX_DBM is applied
    RU106BW160_CE_FRAME_POWER_MAX_DBM[15..8] - (RW) Small RU484 in DBW160 Center corner Maximum TX power dBm 
                                     RU106BW160_HI_FRAME_POWER_MAX_DBM is applied
    RU106BW160_HI_FRAME_POWER_MAX_DBM[23..16] - (RW) Small RU484 in DBW160 Higher corner Maximum TX power dBm 
                                     RU106BW160_HI_FRAME_POWER_MAX_DBM is applied
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_HI_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR12_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_HI_FRAME_POWER_MAX_DBM_MASK 0x00FF0000                // RU106BW160_HI_FRAME_POWER_MAX_DBM[23..16]
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_HI_FRAME_POWER_MAX_DBM_SHFT 16
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_CE_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR12_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_CE_FRAME_POWER_MAX_DBM_MASK 0x0000FF00                // RU106BW160_CE_FRAME_POWER_MAX_DBM[15..8]
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_CE_FRAME_POWER_MAX_DBM_SHFT 8
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_LO_FRAME_POWER_MAX_DBM_ADDR BN0_WF_TMAC_TOP_SRU_FP0CR12_ADDR
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_LO_FRAME_POWER_MAX_DBM_MASK 0x000000FF                // RU106BW160_LO_FRAME_POWER_MAX_DBM[7..0]
#define BN0_WF_TMAC_TOP_SRU_FP0CR12_RU106BW160_LO_FRAME_POWER_MAX_DBM_SHFT 0

/* =====================================================================================

  ---DUCR4 (0x820E4000 + 0x330)---

    DUR_CR1_UNIT[2..0]           - (RW) DUR_CR1 Unit
                                     3'h0: 1us
                                     3'h1: 2us
                                     3'h2: 4us
                                     3'h3: 8us
                                     3'h4: 16us
                                     3'h5: 32us
                                     3'h6: 64us
                                     3'h7: 128us
    DUR_CR2_UNIT[5..3]           - (RW) DUR_CR2 Unit
                                     the sam as DUR_CR1_UNIT
    DUR_CR3_UNIT[8..6]           - (RW) DUR_CR3 Unit
                                     the sam as DUR_CR1_UNIT
    DUR_CR4_UNIT[11..9]          - (RW) DUR_CR4 Unit
                                     the sam as DUR_CR1_UNIT
    DUR_CR5_UNIT[14..12]         - (RW) DUR_CR5 Unit
                                     the sam as DUR_CR1_UNIT
    RESERVED15[15]               - (RO) Reserved bits
    DUR_CR6_UNIT[18..16]         - (RW) DUR_CR6 Unit
                                     the sam as DUR_CR1_UNIT
    DUR_CR7_UNIT[21..19]         - (RW) DUR_CR7 Unit
                                     the sam as DUR_CR1_UNIT
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR7_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR7_UNIT_MASK                0x00380000                // DUR_CR7_UNIT[21..19]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR7_UNIT_SHFT                19
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR6_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR6_UNIT_MASK                0x00070000                // DUR_CR6_UNIT[18..16]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR6_UNIT_SHFT                16
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR5_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR5_UNIT_MASK                0x00007000                // DUR_CR5_UNIT[14..12]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR5_UNIT_SHFT                12
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR4_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR4_UNIT_MASK                0x00000E00                // DUR_CR4_UNIT[11..9]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR4_UNIT_SHFT                9
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR3_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR3_UNIT_MASK                0x000001C0                // DUR_CR3_UNIT[8..6]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR3_UNIT_SHFT                6
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR2_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR2_UNIT_MASK                0x00000038                // DUR_CR2_UNIT[5..3]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR2_UNIT_SHFT                3
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR1_UNIT_ADDR                BN0_WF_TMAC_TOP_DUCR4_ADDR
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR1_UNIT_MASK                0x00000007                // DUR_CR1_UNIT[2..0]
#define BN0_WF_TMAC_TOP_DUCR4_DUR_CR1_UNIT_SHFT                0

/* =====================================================================================

  ---SRTCR0 (0x820E4000 + 0x338)---

    OBSS_PD_MIN[8..0]            - (RW) For non-SRG PPDU (S(7.1))
                                     Use these value and Inter_BSS_PPDU_RSSI to calculate
                                      MaxTxpower
    RESERVED9[11..9]             - (RO) Reserved bits
    OBSS_PD_MIN_SRG[20..12]      - (RW) for SRG PPDU (S(7.1))
                                     Use these value and Inter_BSS_PPDU_RSSI to calculate 
                                     MaxTXPower
    SR_RESP_TXPWR_MODE[21]       - (RW) SR power restriction for response packet
                                     0: No restriction
                                     1: follow TX Power restriction
    SR_TXPWR_RESTRIC_MODE[23..22] - (RW) SR power restriction mode
                                     00: No restriction No txpower limitation when we execute SR
                                     01: Follow restriction (1) Follow spec SR txpower limitation
                                     10: Follow restriction (2) Follow our SR txpower limitation
    OBSS_TXPWR_REF[31..24]       - (RW) Spec default value (S(6.1))

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_TXPWR_REF_ADDR             BN0_WF_TMAC_TOP_SRTCR0_ADDR
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_TXPWR_REF_MASK             0xFF000000                // OBSS_TXPWR_REF[31..24]
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_TXPWR_REF_SHFT             24
#define BN0_WF_TMAC_TOP_SRTCR0_SR_TXPWR_RESTRIC_MODE_ADDR      BN0_WF_TMAC_TOP_SRTCR0_ADDR
#define BN0_WF_TMAC_TOP_SRTCR0_SR_TXPWR_RESTRIC_MODE_MASK      0x00C00000                // SR_TXPWR_RESTRIC_MODE[23..22]
#define BN0_WF_TMAC_TOP_SRTCR0_SR_TXPWR_RESTRIC_MODE_SHFT      22
#define BN0_WF_TMAC_TOP_SRTCR0_SR_RESP_TXPWR_MODE_ADDR         BN0_WF_TMAC_TOP_SRTCR0_ADDR
#define BN0_WF_TMAC_TOP_SRTCR0_SR_RESP_TXPWR_MODE_MASK         0x00200000                // SR_RESP_TXPWR_MODE[21]
#define BN0_WF_TMAC_TOP_SRTCR0_SR_RESP_TXPWR_MODE_SHFT         21
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_SRG_ADDR            BN0_WF_TMAC_TOP_SRTCR0_ADDR
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_SRG_MASK            0x001FF000                // OBSS_PD_MIN_SRG[20..12]
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_SRG_SHFT            12
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_ADDR                BN0_WF_TMAC_TOP_SRTCR0_ADDR
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_MASK                0x000001FF                // OBSS_PD_MIN[8..0]
#define BN0_WF_TMAC_TOP_SRTCR0_OBSS_PD_MIN_SHFT                0

/* =====================================================================================

  ---TFCR6 (0x820E4000 + 0x340)---

    BSSID00_CFO_IDX[3..0]        - (RW) CFO Index for BSSID00
    BSSID01_CFO_IDX[7..4]        - (RW) CFO Index for BSSID01
    BSSID02_CFO_IDX[11..8]       - (RW) CFO Index for BSSID02
    BSSID03_CFO_IDX[15..12]      - (RW) CFO Index for BSSID03
    BSSIDXX_CFO_EN[19..16]       - (RW) CFO Index enable
                                     bit[3]: BSSID03
                                     bit[2]: BSSID02
                                     bit[1]: BSSID01
                                     bit[0]: BSSID00
    RESERVED20[23..20]           - (RO) Reserved bits
    TXCFO_TB_HETB_EN[24]         - (RW) CFO enabled control for Trigger -Response HE_TB Mod
    TXCFO_TB_OFDM_EN[25]         - (RW) CFO enabled control for Trigger -Response Hon-HT OFDM Mod
    TXCFO_NTB_HEMU_EN[26]        - (RW) CFO enabled control for Non-Trigger -Response HE_MU Mod
    TXCFO_NTB_HESU_ERSU_EN[27]   - (RW) CFO enabled control for Non-Trigger -Response HE_SU/HE_ER_SU Mod
    TXCFO_NTB_VHT_EN[28]         - (RW) CFO enabled control for Non-Trigger -Response VHT Mod
    TXCFO_NTB_HT_EN[29]          - (RW) CFO enabled control for Non-Trigger -Response HT Mod
    TXCFO_NTB_OFDM_EN[30]        - (RW) CFO enabled control for Non-Trigger -Response Non-HT OFDM Mod
    TXCFO_NTB_CCK_EN[31]         - (RW) CFO enabled control for Non-Trigger -Response CCK Mod

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_CCK_EN_ADDR            BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_CCK_EN_MASK            0x80000000                // TXCFO_NTB_CCK_EN[31]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_CCK_EN_SHFT            31
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_OFDM_EN_ADDR           BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_OFDM_EN_MASK           0x40000000                // TXCFO_NTB_OFDM_EN[30]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_OFDM_EN_SHFT           30
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HT_EN_ADDR             BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HT_EN_MASK             0x20000000                // TXCFO_NTB_HT_EN[29]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HT_EN_SHFT             29
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_VHT_EN_ADDR            BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_VHT_EN_MASK            0x10000000                // TXCFO_NTB_VHT_EN[28]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_VHT_EN_SHFT            28
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HESU_ERSU_EN_ADDR      BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HESU_ERSU_EN_MASK      0x08000000                // TXCFO_NTB_HESU_ERSU_EN[27]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HESU_ERSU_EN_SHFT      27
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HEMU_EN_ADDR           BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HEMU_EN_MASK           0x04000000                // TXCFO_NTB_HEMU_EN[26]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_NTB_HEMU_EN_SHFT           26
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_OFDM_EN_ADDR            BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_OFDM_EN_MASK            0x02000000                // TXCFO_TB_OFDM_EN[25]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_OFDM_EN_SHFT            25
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_HETB_EN_ADDR            BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_HETB_EN_MASK            0x01000000                // TXCFO_TB_HETB_EN[24]
#define BN0_WF_TMAC_TOP_TFCR6_TXCFO_TB_HETB_EN_SHFT            24
#define BN0_WF_TMAC_TOP_TFCR6_BSSIDXX_CFO_EN_ADDR              BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_BSSIDXX_CFO_EN_MASK              0x000F0000                // BSSIDXX_CFO_EN[19..16]
#define BN0_WF_TMAC_TOP_TFCR6_BSSIDXX_CFO_EN_SHFT              16
#define BN0_WF_TMAC_TOP_TFCR6_BSSID03_CFO_IDX_ADDR             BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_BSSID03_CFO_IDX_MASK             0x0000F000                // BSSID03_CFO_IDX[15..12]
#define BN0_WF_TMAC_TOP_TFCR6_BSSID03_CFO_IDX_SHFT             12
#define BN0_WF_TMAC_TOP_TFCR6_BSSID02_CFO_IDX_ADDR             BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_BSSID02_CFO_IDX_MASK             0x00000F00                // BSSID02_CFO_IDX[11..8]
#define BN0_WF_TMAC_TOP_TFCR6_BSSID02_CFO_IDX_SHFT             8
#define BN0_WF_TMAC_TOP_TFCR6_BSSID01_CFO_IDX_ADDR             BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_BSSID01_CFO_IDX_MASK             0x000000F0                // BSSID01_CFO_IDX[7..4]
#define BN0_WF_TMAC_TOP_TFCR6_BSSID01_CFO_IDX_SHFT             4
#define BN0_WF_TMAC_TOP_TFCR6_BSSID00_CFO_IDX_ADDR             BN0_WF_TMAC_TOP_TFCR6_ADDR
#define BN0_WF_TMAC_TOP_TFCR6_BSSID00_CFO_IDX_MASK             0x0000000F                // BSSID00_CFO_IDX[3..0]
#define BN0_WF_TMAC_TOP_TFCR6_BSSID00_CFO_IDX_SHFT             0

/* =====================================================================================

  ---DUCR6 (0x820E4000 + 0x344)---

    BSSID00_TXOP_DUR_DIS[0]      - (RW) When transmit HE PPDU, assign UNSPECIFIED value to TXVECTOR.TXOP_DURATION field for 00
                                     bit[3] : for BSSID03
                                     bit[2] : for BSSID02
                                     bit[1] : for BSSID01
                                     bit[0] : for BSSID00
    BSSID01_TXOP_DUR_DIS[1]      - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID01
    BSSID02_TXOP_DUR_DIS[2]      - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID02
    BSSID03_TXOP_DUR_DIS[3]      - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID03
    RESERVED4[15..4]             - (RO) Reserved bits
    BSSID1X_TXOP_DUR_DIS[31..16] - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID1F~10

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DUCR6_BSSID1X_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR6_ADDR
#define BN0_WF_TMAC_TOP_DUCR6_BSSID1X_TXOP_DUR_DIS_MASK        0xFFFF0000                // BSSID1X_TXOP_DUR_DIS[31..16]
#define BN0_WF_TMAC_TOP_DUCR6_BSSID1X_TXOP_DUR_DIS_SHFT        16
#define BN0_WF_TMAC_TOP_DUCR6_BSSID03_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR6_ADDR
#define BN0_WF_TMAC_TOP_DUCR6_BSSID03_TXOP_DUR_DIS_MASK        0x00000008                // BSSID03_TXOP_DUR_DIS[3]
#define BN0_WF_TMAC_TOP_DUCR6_BSSID03_TXOP_DUR_DIS_SHFT        3
#define BN0_WF_TMAC_TOP_DUCR6_BSSID02_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR6_ADDR
#define BN0_WF_TMAC_TOP_DUCR6_BSSID02_TXOP_DUR_DIS_MASK        0x00000004                // BSSID02_TXOP_DUR_DIS[2]
#define BN0_WF_TMAC_TOP_DUCR6_BSSID02_TXOP_DUR_DIS_SHFT        2
#define BN0_WF_TMAC_TOP_DUCR6_BSSID01_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR6_ADDR
#define BN0_WF_TMAC_TOP_DUCR6_BSSID01_TXOP_DUR_DIS_MASK        0x00000002                // BSSID01_TXOP_DUR_DIS[1]
#define BN0_WF_TMAC_TOP_DUCR6_BSSID01_TXOP_DUR_DIS_SHFT        1
#define BN0_WF_TMAC_TOP_DUCR6_BSSID00_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR6_ADDR
#define BN0_WF_TMAC_TOP_DUCR6_BSSID00_TXOP_DUR_DIS_MASK        0x00000001                // BSSID00_TXOP_DUR_DIS[0]
#define BN0_WF_TMAC_TOP_DUCR6_BSSID00_TXOP_DUR_DIS_SHFT        0

/* =====================================================================================

  ---DUCR7 (0x820E4000 + 0x348)---

    BSSID2X_TXOP_DUR_DIS[15..0]  - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID2F~20
    BSSID37_20_TXOP_DUR_DIS[23..16] - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID37~30
    BSSID3F_38_TXOP_DUR_DIS[31..24] - (RW) the same as BSSID00_TXOP_DUR_DIS for BSSID3F~38

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_DUCR7_BSSID3F_38_TXOP_DUR_DIS_ADDR     BN0_WF_TMAC_TOP_DUCR7_ADDR
#define BN0_WF_TMAC_TOP_DUCR7_BSSID3F_38_TXOP_DUR_DIS_MASK     0xFF000000                // BSSID3F_38_TXOP_DUR_DIS[31..24]
#define BN0_WF_TMAC_TOP_DUCR7_BSSID3F_38_TXOP_DUR_DIS_SHFT     24
#define BN0_WF_TMAC_TOP_DUCR7_BSSID37_20_TXOP_DUR_DIS_ADDR     BN0_WF_TMAC_TOP_DUCR7_ADDR
#define BN0_WF_TMAC_TOP_DUCR7_BSSID37_20_TXOP_DUR_DIS_MASK     0x00FF0000                // BSSID37_20_TXOP_DUR_DIS[23..16]
#define BN0_WF_TMAC_TOP_DUCR7_BSSID37_20_TXOP_DUR_DIS_SHFT     16
#define BN0_WF_TMAC_TOP_DUCR7_BSSID2X_TXOP_DUR_DIS_ADDR        BN0_WF_TMAC_TOP_DUCR7_ADDR
#define BN0_WF_TMAC_TOP_DUCR7_BSSID2X_TXOP_DUR_DIS_MASK        0x0000FFFF                // BSSID2X_TXOP_DUR_DIS[15..0]
#define BN0_WF_TMAC_TOP_DUCR7_BSSID2X_TXOP_DUR_DIS_SHFT        0

/* =====================================================================================

  ---SRTCR2 (0x820E4000 + 0x34C)---

    BSSID00_SPATIAL_REUSE[3..0]  - (RW) Spatial Reuse for TXV
                                     0: SRP_DISALLOW
                                     13: SR_RESTRICTED
                                     14: SR_DELAY
                                     15: SRP_AND_NON-SRG_OBSS-PD_PROHIBITED
                                     Others: Reserved
    BSSID01_SPATIAL_REUSE[7..4]  - (RW) For BSSID01, the same as BSSID00_SPATIAL_RESUE
    BSSID02_SPATIAL_REUSE[11..8] - (RW) For BSSID02, the same as BSSID00_SPATIAL_RESUE
    BSSID03_SPATIAL_REUSE[15..12] - (RW) For BSSID03, the same as BSSID00_SPATIAL_RESUE
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID03_SPATIAL_REUSE_ADDR      BN0_WF_TMAC_TOP_SRTCR2_ADDR
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID03_SPATIAL_REUSE_MASK      0x0000F000                // BSSID03_SPATIAL_REUSE[15..12]
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID03_SPATIAL_REUSE_SHFT      12
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID02_SPATIAL_REUSE_ADDR      BN0_WF_TMAC_TOP_SRTCR2_ADDR
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID02_SPATIAL_REUSE_MASK      0x00000F00                // BSSID02_SPATIAL_REUSE[11..8]
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID02_SPATIAL_REUSE_SHFT      8
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID01_SPATIAL_REUSE_ADDR      BN0_WF_TMAC_TOP_SRTCR2_ADDR
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID01_SPATIAL_REUSE_MASK      0x000000F0                // BSSID01_SPATIAL_REUSE[7..4]
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID01_SPATIAL_REUSE_SHFT      4
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID00_SPATIAL_REUSE_ADDR      BN0_WF_TMAC_TOP_SRTCR2_ADDR
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID00_SPATIAL_REUSE_MASK      0x0000000F                // BSSID00_SPATIAL_REUSE[3..0]
#define BN0_WF_TMAC_TOP_SRTCR2_BSSID00_SPATIAL_REUSE_SHFT      0

/* =====================================================================================

  ---SRTCR3 (0x820E4000 + 0x350)---

    BSSID10_17_SPATIAL_REUSE[31..0] - (RW) For BSSID10 ~ BSSID17, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID10
                                     bit[7:4]: for BSSID11
                                     bit[11:8]: for BSSID12
                                     bit[15:12]: for BSSID13
                                     bit[19:16]: for BSSID14
                                     bit[23:20]: for BSSID15
                                     bit[27:24]: for BSSID16
                                     bit[31:28]: for BSSID17

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR3_BSSID10_17_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR3_ADDR
#define BN0_WF_TMAC_TOP_SRTCR3_BSSID10_17_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID10_17_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR3_BSSID10_17_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---SRTCR4 (0x820E4000 + 0x354)---

    BSSID18_1F_SPATIAL_REUSE[31..0] - (RW) For BSSID18 ~ BSSID1F, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID18
                                     bit[7:4]: for BSSID19
                                     bit[11:8]: for BSSID1A
                                     bit[15:12]: for BSSID1B
                                     bit[19:16]: for BSSID1C
                                     bit[23:20]: for BSSID1D
                                     bit[27:24]: for BSSID1E
                                     bit[31:28]: for BSSID1F

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR4_BSSID18_1F_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR4_ADDR
#define BN0_WF_TMAC_TOP_SRTCR4_BSSID18_1F_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID18_1F_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR4_BSSID18_1F_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---SRTCR5 (0x820E4000 + 0x358)---

    BSSID20_27_SPATIAL_REUSE[31..0] - (RW) For BSSID20 ~ BSSID27, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID20
                                     bit[7:4]: for BSSID21
                                     bit[11:8]: for BSSID22
                                     bit[15:12]: for BSSID23
                                     bit[19:16]: for BSSID24
                                     bit[23:20]: for BSSID25
                                     bit[27:24]: for BSSID26
                                     bit[31:28]: for BSSID27

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR5_BSSID20_27_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR5_ADDR
#define BN0_WF_TMAC_TOP_SRTCR5_BSSID20_27_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID20_27_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR5_BSSID20_27_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---SRTCR6 (0x820E4000 + 0x35C)---

    BSSID28_2F_SPATIAL_REUSE[31..0] - (RW) For BSSID28 ~ BSSID2F, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID28
                                     bit[7:4]: for BSSID29
                                     bit[11:8]: for BSSID2A
                                     bit[15:12]: for BSSID2B
                                     bit[19:16]: for BSSID2C
                                     bit[23:20]: for BSSID2D
                                     bit[27:24]: for BSSID2E
                                     bit[31:28]: for BSSID2F

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR6_BSSID28_2F_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR6_ADDR
#define BN0_WF_TMAC_TOP_SRTCR6_BSSID28_2F_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID28_2F_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR6_BSSID28_2F_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---SRTCR7 (0x820E4000 + 0x360)---

    BSSID30_37_SPATIAL_REUSE[31..0] - (RW) For BSSID30 ~ BSSID37, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID30
                                     bit[7:4]: for BSSID31
                                     bit[11:8]: for BSSID32
                                     bit[15:12]: for BSSID33
                                     bit[19:16]: for BSSID34
                                     bit[23:20]: for BSSID35
                                     bit[27:24]: for BSSID36
                                     bit[31:28]: for BSSID37

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR7_BSSID30_37_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR7_ADDR
#define BN0_WF_TMAC_TOP_SRTCR7_BSSID30_37_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID30_37_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR7_BSSID30_37_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---SRTCR8 (0x820E4000 + 0x364)---

    BSSID38_3F_SPATIAL_REUSE[31..0] - (RW) For BSSID38 ~ BSSID3F, the same as BSSID00_SPATIAL_RESUE
                                     bit[3:0]: for BSSID38
                                     bit[7:4]: for BSSID39
                                     bit[11:8]: for BSSID3A
                                     bit[15:12]: for BSSID3B
                                     bit[19:16]: for BSSID3C
                                     bit[23:20]: for BSSID3D
                                     bit[27:24]: for BSSID3E
                                     bit[31:28]: for BSSID3F

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_SRTCR8_BSSID38_3F_SPATIAL_REUSE_ADDR   BN0_WF_TMAC_TOP_SRTCR8_ADDR
#define BN0_WF_TMAC_TOP_SRTCR8_BSSID38_3F_SPATIAL_REUSE_MASK   0xFFFFFFFF                // BSSID38_3F_SPATIAL_REUSE[31..0]
#define BN0_WF_TMAC_TOP_SRTCR8_BSSID38_3F_SPATIAL_REUSE_SHFT   0

/* =====================================================================================

  ---TTRCR0 (0x820E4000 + 0x370)---

    TF_COMINFO_B31B0[31..0]      - (RW) Trigger Frame's Common Info bit[31:0]

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR0_TF_COMINFO_B31B0_ADDR           BN0_WF_TMAC_TOP_TTRCR0_ADDR
#define BN0_WF_TMAC_TOP_TTRCR0_TF_COMINFO_B31B0_MASK           0xFFFFFFFF                // TF_COMINFO_B31B0[31..0]
#define BN0_WF_TMAC_TOP_TTRCR0_TF_COMINFO_B31B0_SHFT           0

/* =====================================================================================

  ---TTRCR1 (0x820E4000 + 0x374)---

    TF_COMINFO_B63B32[31..0]     - (RW) Trigger Frame's Common Info bit[63:32]

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR1_TF_COMINFO_B63B32_ADDR          BN0_WF_TMAC_TOP_TTRCR1_ADDR
#define BN0_WF_TMAC_TOP_TTRCR1_TF_COMINFO_B63B32_MASK          0xFFFFFFFF                // TF_COMINFO_B63B32[31..0]
#define BN0_WF_TMAC_TOP_TTRCR1_TF_COMINFO_B63B32_SHFT          0

/* =====================================================================================

  ---TTRCR2 (0x820E4000 + 0x378)---

    TF_USRINFO_B31B0[31..0]      - (RW) Trigger Frame's User Info bit[31:0]

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR2_TF_USRINFO_B31B0_ADDR           BN0_WF_TMAC_TOP_TTRCR2_ADDR
#define BN0_WF_TMAC_TOP_TTRCR2_TF_USRINFO_B31B0_MASK           0xFFFFFFFF                // TF_USRINFO_B31B0[31..0]
#define BN0_WF_TMAC_TOP_TTRCR2_TF_USRINFO_B31B0_SHFT           0

/* =====================================================================================

  ---TTRCR3 (0x820E4000 + 0x37C)---

    TF_USRINFO_B39B32[7..0]      - (RW) Trigger Frame's User Info bit[7:0]
    RESERVED8[30..8]             - (RO) Reserved bits
    TF_RESP_TEST_MODE[31]        - (RW) Trigger Response Test Mode Enable
                                     0: enable test mode
                                     1: disable test mode

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR3_TF_RESP_TEST_MODE_ADDR          BN0_WF_TMAC_TOP_TTRCR3_ADDR
#define BN0_WF_TMAC_TOP_TTRCR3_TF_RESP_TEST_MODE_MASK          0x80000000                // TF_RESP_TEST_MODE[31]
#define BN0_WF_TMAC_TOP_TTRCR3_TF_RESP_TEST_MODE_SHFT          31
#define BN0_WF_TMAC_TOP_TTRCR3_TF_USRINFO_B39B32_ADDR          BN0_WF_TMAC_TOP_TTRCR3_ADDR
#define BN0_WF_TMAC_TOP_TTRCR3_TF_USRINFO_B39B32_MASK          0x000000FF                // TF_USRINFO_B39B32[7..0]
#define BN0_WF_TMAC_TOP_TTRCR3_TF_USRINFO_B39B32_SHFT          0

/* =====================================================================================

  ---TTRCR4 (0x820E4000 + 0x380)---

    TF_RX_RSSI_20M_B26B0[26..0]  - (RW) Trigger Frame's RX RSSI per 20MHz bit[26:0]
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR4_TF_RX_RSSI_20M_B26B0_ADDR       BN0_WF_TMAC_TOP_TTRCR4_ADDR
#define BN0_WF_TMAC_TOP_TTRCR4_TF_RX_RSSI_20M_B26B0_MASK       0x07FFFFFF                // TF_RX_RSSI_20M_B26B0[26..0]
#define BN0_WF_TMAC_TOP_TTRCR4_TF_RX_RSSI_20M_B26B0_SHFT       0

/* =====================================================================================

  ---TTRCR5 (0x820E4000 + 0x384)---

    TF_RX_RSSI_20M_B53B27[26..0] - (RW) Trigger Frame's RX RSSI per 20MHz bit[53:27]
    RESERVED27[31..27]           - (RO) Reserved bits

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR5_TF_RX_RSSI_20M_B53B27_ADDR      BN0_WF_TMAC_TOP_TTRCR5_ADDR
#define BN0_WF_TMAC_TOP_TTRCR5_TF_RX_RSSI_20M_B53B27_MASK      0x07FFFFFF                // TF_RX_RSSI_20M_B53B27[26..0]
#define BN0_WF_TMAC_TOP_TTRCR5_TF_RX_RSSI_20M_B53B27_SHFT      0

/* =====================================================================================

  ---TTRCR6 (0x820E4000 + 0x388)---

    TF_RX_RSSI_20M_B71B54[17..0] - (RW) Trigger Frame's RX RSSI per 20MHz bit[71:54]
    RESERVED18[23..18]           - (RO) Reserved bits
    TF_RX_BWD_20M[31..24]        - (RW) Trigger Frame's RX BWD indicator

 =====================================================================================*/
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_BWD_20M_ADDR              BN0_WF_TMAC_TOP_TTRCR6_ADDR
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_BWD_20M_MASK              0xFF000000                // TF_RX_BWD_20M[31..24]
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_BWD_20M_SHFT              24
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_RSSI_20M_B71B54_ADDR      BN0_WF_TMAC_TOP_TTRCR6_ADDR
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_RSSI_20M_B71B54_MASK      0x0003FFFF                // TF_RX_RSSI_20M_B71B54[17..0]
#define BN0_WF_TMAC_TOP_TTRCR6_TF_RX_RSSI_20M_B71B54_SHFT      0

#ifdef __cplusplus
}
#endif

#endif // __BN0_WF_TMAC_TOP_REGS_H__
